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From: Fabiano Rosas <farosas@suse.de>
To: "Alex Bennée" <alex.bennee@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, "Alex Bennée" <alex.bennee@linaro.org>,
	"Ilias Apalodimas" <ilias.apalodimas@linaro.org>,
	"Peter Maydell" <peter.maydell@linaro.org>
Subject: Re: [RFC PATCH] target/arm: disable FEAT_SME if we turn off SVE
Date: Tue, 07 Feb 2023 10:45:20 -0300	[thread overview]
Message-ID: <87cz6loahb.fsf@suse.de> (raw)
In-Reply-To: <20230203100551.2445547-1-alex.bennee@linaro.org>

Alex Bennée <alex.bennee@linaro.org> writes:

> Before this change booting a -cpu max,sve=off would trigger and
> assert:
>
>   qemu-system-aarch64: ../../target/arm/helper.c:6647: sve_vqm1_for_el_sm: Assertion `sm' failed.
>
> when the guest attempts to write to SMCR which shouldn't even exist if
> SVE has been turned off.
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
> ---
>  target/arm/cpu64.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 0e021960fb..a38d43421a 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -409,6 +409,13 @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)
>      t = cpu->isar.id_aa64pfr0;
>      t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
>      cpu->isar.id_aa64pfr0 = t;
> +
> +    /* FEAT_SME requires SVE, so disable it if no SVE */
> +    if (!value) {
> +        t = cpu->isar.id_aa64pfr1;
> +        t = FIELD_DP64(t, ID_AA64PFR1, SME, 0);
> +        cpu->isar.id_aa64pfr1 = t;
> +    }

What about -cpu max,sve=off,sme=on ?



  reply	other threads:[~2023-02-07 13:46 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-03 10:05 [RFC PATCH] target/arm: disable FEAT_SME if we turn off SVE Alex Bennée
2023-02-07 13:45 ` Fabiano Rosas [this message]
2023-02-07 15:09   ` Alex Bennée
2023-02-10 14:07     ` Markus Armbruster
2023-02-10 14:39       ` Peter Maydell

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