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Tue, 17 Jan 2023 10:34:37 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 436A51FFB7; Tue, 17 Jan 2023 18:34:37 +0000 (GMT) References: <20230109014248.2894281-1-richard.henderson@linaro.org> <20230109014248.2894281-21-richard.henderson@linaro.org> User-agent: mu4e 1.9.15; emacs 29.0.60 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: qemu-devel@nongnu.org Subject: Re: [PATCH v2 20/22] tcg/arm: Implement direct branch for goto_tb Date: Tue, 17 Jan 2023 18:33:24 +0000 In-reply-to: <20230109014248.2894281-21-richard.henderson@linaro.org> Message-ID: <87cz7d103m.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Richard Henderson writes: > Now that tcg can handle direct and indirect goto_tb > simultaneously, we can optimistically leave space for > a direct branch and fall back to loading the pointer > from the TB for an indirect branch. > > Signed-off-by: Richard Henderson > --- > tcg/arm/tcg-target.c.inc | 52 ++++++++++++++++++++++++++++------------ > 1 file changed, 37 insertions(+), 15 deletions(-) > > diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc > index e1e1c2620d..794ed8c3a2 100644 > --- a/tcg/arm/tcg-target.c.inc > +++ b/tcg/arm/tcg-target.c.inc > @@ -135,6 +135,8 @@ typedef enum { > ARITH_BIC =3D 0xe << 21, > ARITH_MVN =3D 0xf << 21, >=20=20 > + INSN_B =3D 0x0a000000, > + > INSN_CLZ =3D 0x016f0f10, > INSN_RBIT =3D 0x06ff0f30, >=20=20 > @@ -546,7 +548,7 @@ static bool tcg_target_const_match(int64_t val, TCGTy= pe type, int ct) >=20=20 > static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset) > { > - tcg_out32(s, (cond << 28) | 0x0a000000 | > + tcg_out32(s, (cond << 28) | INSN_B | > (((offset - 8) >> 2) & 0x00ffffff)); deposit32? > } >=20=20 > @@ -1941,32 +1943,52 @@ static void tcg_out_exit_tb(TCGContext *s, uintpt= r_t arg) >=20=20 > static void tcg_out_goto_tb(TCGContext *s, int which) > { > - /* Indirect jump method */ > - intptr_t ptr, dif, dil; > - TCGReg base =3D TCG_REG_PC; > + uintptr_t i_addr; > + intptr_t i_disp; >=20=20 > - ptr =3D get_jmp_target_addr(s, which); > - dif =3D tcg_pcrel_diff(s, (void *)ptr) - 8; > - dil =3D sextract32(dif, 0, 12); > - if (dif !=3D dil) { > + /* Direct branch will be patched by tb_target_set_jmp_target. */ > + set_jmp_insn_offset(s, which); > + tcg_out32(s, INSN_NOP); > + > + /* When branch is out of range, fall through to indirect. */ > + i_addr =3D get_jmp_target_addr(s, which); > + i_disp =3D tcg_pcrel_diff(s, (void *)i_addr) - 8; > + tcg_debug_assert(i_disp < 0); > + if (i_disp >=3D -0xfff) { > + tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp); > + } else { > /* > * The TB is close, but outside the 12 bits addressable by > * the load. We can extend this to 20 bits with a sub of a > - * shifted immediate from pc. In the vastly unlikely event > - * the code requires more than 1MB, we'll use 2 insns and > - * be no worse off. > + * shifted immediate from pc. > */ > - base =3D TCG_REG_R0; > - tcg_out_movi32(s, COND_AL, base, ptr - dil); > + int h =3D -i_disp; > + int l =3D h & 0xfff; > + > + h =3D encode_imm_nofail(h - l); > + tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h= ); > + tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l); > } > - tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, base, dil); > set_jmp_reset_offset(s, which); > } >=20=20 > void tb_target_set_jmp_target(const TranslationBlock *tb, int n, > uintptr_t jmp_rx, uintptr_t jmp_rw) > { > - /* Always indirect, nothing to do */ > + uintptr_t addr =3D tb->jmp_target_addr[n]; > + ptrdiff_t offset =3D addr - (jmp_rx + 8); > + tcg_insn_unit insn; > + > + /* Either directly branch, or fall through to indirect branch. */ > + if (offset =3D=3D sextract64(offset, 0, 26)) { > + /* B */ > + insn =3D (COND_AL << 28) | INSN_B | ((offset >> 2) & > 0x00ffffff); deposit32 > + } else { > + insn =3D INSN_NOP; > + } > + > + qatomic_set((uint32_t *)jmp_rw, insn); > + flush_idcache_range(jmp_rx, jmp_rw, 4); > } >=20=20 > static void tcg_out_op(TCGContext *s, TCGOpcode opc, Otherwise: Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro