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Fri, 24 Jun 2022 18:34:46 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AB73EBE04F; Fri, 24 Jun 2022 18:34:45 +0000 (GMT) Received: from localhost (unknown [9.160.103.235]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTPS; Fri, 24 Jun 2022 18:34:45 +0000 (GMT) From: Fabiano Rosas To: Leandro Lupori , qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, richard.henderson@linaro.org, Leandro Lupori Subject: Re: [PATCH v2 2/3] target/ppc: Improve Radix xlate level validation In-Reply-To: <20220624171653.143740-3-leandro.lupori@eldorado.org.br> References: <20220624171653.143740-1-leandro.lupori@eldorado.org.br> <20220624171653.143740-3-leandro.lupori@eldorado.org.br> Date: Fri, 24 Jun 2022 15:34:43 -0300 Message-ID: <87czexc3lo.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 87hD8VgFRKHdoIgJS38BeFdoabdmZKCH X-Proofpoint-GUID: -r80ApQ32qdUkHFpSg_WkfVzYBYztaZQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-06-24_08,2022-06-23_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 spamscore=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 priorityscore=1501 bulkscore=0 adultscore=0 phishscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206240072 Received-SPF: pass client-ip=148.163.158.5; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Leandro Lupori writes: > Check if the number and size of Radix levels are valid on > POWER9/POWER10 CPUs, according to the supported Radix Tree > Configurations described in their User Manuals. > > Signed-off-by: Leandro Lupori > --- > target/ppc/mmu-radix64.c | 51 +++++++++++++++++++++++++++++++--------- > 1 file changed, 40 insertions(+), 11 deletions(-) > > diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c > index 9a8a2e2875..339cf5b4d8 100644 > --- a/target/ppc/mmu-radix64.c > +++ b/target/ppc/mmu-radix64.c > @@ -236,17 +236,39 @@ static void ppc_radix64_set_rc(PowerPCCPU *cpu, MMUAccessType access_type, > } > } > > +static bool ppc_radix64_is_valid_level(int level, int psize, uint64_t nls) > +{ > + /* > + * Check if this is a valid level, according to POWER9 and POWER10 > + * Processor User's Manuals, sections 4.10.4.1 and 5.10.6.1, respectively: > + * Supported Radix Tree Configurations and Resulting Page Sizes. > + * > + * NOTE: these checks are valid for POWER9 and POWER10 CPUs only. If > + * new CPUs that support other Radix configurations are added > + * (e.g., Microwatt), then a new method should be added to > + * PowerPCCPUClass, with this function being the POWER9/POWER10 > + * implementation. > + */ Sorry, this got too specific now. I could not respond in time before you sent the v2. Let's cut the mentions to the code: Note: these checks are specific to POWER9 and POWER10 CPUs. Any future CPUs that supports a different Radix MMU configuration will need their own implementation. > + switch (level) { > + case 0: /* Root Page Dir */ > + return psize == 52 && nls == 13; > + case 1: > + case 2: > + return nls == 9; > + case 3: > + return nls == 9 || nls == 5; > + default: > + qemu_log_mask(LOG_GUEST_ERROR, "invalid radix level: %d\n", level); > + return false; > + } > +} > + > static int ppc_radix64_next_level(AddressSpace *as, vaddr eaddr, > uint64_t *pte_addr, uint64_t *nls, > int *psize, uint64_t *pte, int *fault_cause) > { > uint64_t index, pde; > > - if (*nls < 5) { /* Directory maps less than 2**5 entries */ > - *fault_cause |= DSISR_R_BADCONFIG; > - return 1; > - } > - > /* Read page entry from guest address space */ > pde = ldq_phys(as, *pte_addr); > if (!(pde & R_PTE_VALID)) { /* Invalid Entry */ > @@ -270,12 +292,8 @@ static int ppc_radix64_walk_tree(AddressSpace *as, vaddr eaddr, > hwaddr *raddr, int *psize, uint64_t *pte, > int *fault_cause, hwaddr *pte_addr) > { > - uint64_t index, pde, rpn , mask; > - > - if (nls < 5) { /* Directory maps less than 2**5 entries */ > - *fault_cause |= DSISR_R_BADCONFIG; > - return 1; > - } > + uint64_t index, pde, rpn, mask; > + int level = 0; > > index = eaddr >> (*psize - nls); /* Shift */ > index &= ((1UL << nls) - 1); /* Mask */ > @@ -283,6 +301,11 @@ static int ppc_radix64_walk_tree(AddressSpace *as, vaddr eaddr, > do { > int ret; > > + if (!ppc_radix64_is_valid_level(level++, *psize, nls)) { > + *fault_cause |= DSISR_R_BADCONFIG; > + return 1; > + } > + > ret = ppc_radix64_next_level(as, eaddr, pte_addr, &nls, psize, &pde, > fault_cause); > if (ret) { > @@ -456,6 +479,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, > } > } else { > uint64_t rpn, mask; > + int level = 0; > > index = (eaddr & R_EADDR_MASK) >> (*g_page_size - nls); /* Shift */ > index &= ((1UL << nls) - 1); /* Mask */ > @@ -475,6 +499,11 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, > return ret; > } > > + if (!ppc_radix64_is_valid_level(level++, *g_page_size, nls)) { > + fault_cause |= DSISR_R_BADCONFIG; > + return 1; > + } > + > ret = ppc_radix64_next_level(cs->as, eaddr & R_EADDR_MASK, &h_raddr, > &nls, g_page_size, &pte, &fault_cause); > if (ret) {