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Wed, 16 Feb 2022 13:06:31 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4992FAC06F; Wed, 16 Feb 2022 13:06:30 +0000 (GMT) Received: from localhost (unknown [9.211.144.50]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTPS; Wed, 16 Feb 2022 13:06:29 +0000 (GMT) From: Fabiano Rosas To: David Gibson Subject: Re: [PATCH 26/27] target/ppc: cpu_init: Move check_pow and QOM macros to a header In-Reply-To: References: <20220215214148.1848266-1-farosas@linux.ibm.com> <20220215214148.1848266-27-farosas@linux.ibm.com> Date: Wed, 16 Feb 2022 10:06:26 -0300 Message-ID: <87czjnx8od.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: txDjv__TIPMn8XWldHLjmcK2kz8X9Dun X-Proofpoint-GUID: 89Zxgy0UJReUSh-kz0XMUd4ph2tHKdVz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-16_06,2022-02-16_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 clxscore=1015 impostorscore=0 phishscore=0 suspectscore=0 malwarescore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2202160076 Received-SPF: pass client-ip=148.163.158.5; envelope-from=farosas@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, clg@kaod.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" David Gibson writes: > On Tue, Feb 15, 2022 at 06:41:47PM -0300, Fabiano Rosas wrote: >> These will need to be accessed from other files once we move the CPUs >> code to separate files. >> >> Signed-off-by: Fabiano Rosas >> --- >> target/ppc/cpu.h | 57 +++++++++++++++++++++++++++++++++++++++++++ >> target/ppc/cpu_init.c | 55 ----------------------------------------- >> 2 files changed, 57 insertions(+), 55 deletions(-) >> >> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h >> index 6a06a7f533..ba0739c43b 100644 >> --- a/target/ppc/cpu.h >> +++ b/target/ppc/cpu.h >> @@ -2733,4 +2733,61 @@ void dump_mmu(CPUPPCState *env); >> void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len); >> void ppc_store_vscr(CPUPPCState *env, uint32_t vscr); >> uint32_t ppc_get_vscr(CPUPPCState *env); >> + >> +/*****************************************************************************/ >> +/* Power management enable checks */ >> +static inline int check_pow_none(CPUPPCState *env) >> +{ >> + return 0; >> +} >> + >> +static inline int check_pow_nocheck(CPUPPCState *env) >> +{ >> + return 1; >> +} >> + >> +static inline int check_pow_hid0(CPUPPCState *env) > > I'm a little nervous about moving this to a more exposed location. By > definition the HID register is implementation dependent, and we can > see immediately below that not all things use the same interpretation > of it in practice. So at the very least it seems like it has a bad > name to be exposed more widely. It also seems like it might better > belong next to the code for the cpus that actually use this version. Good point. Since these are quite simple it might be best to duplicate them when doing the split between the families. I'm doing the same for vscr_init.