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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Laurent Vivier <lvivier@redhat.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
	qemu-devel@nongnu.org,
	Richard Henderson <richard.henderson@linaro.org>
Subject: Re: [Qemu-devel] [PULL 40/55] target/arm: Enable SVE for aarch64-linux-user
Date: Mon, 12 Nov 2018 22:12:58 +0000	[thread overview]
Message-ID: <87d0radjx1.fsf@linaro.org> (raw)
In-Reply-To: <e8d62bcd-f8a9-2a6a-7765-0cf69cc8c1b5@redhat.com>


Laurent Vivier <lvivier@redhat.com> writes:

> On 29/06/2018 16:53, Peter Maydell wrote:
>> From: Richard Henderson <richard.henderson@linaro.org>
>>
>> Enable ARM_FEATURE_SVE for the generic "max" cpu.
>>
>> Tested-by: Alex Bennée <alex.bennee@linaro.org>
>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> Message-id: 20180627043328.11531-35-richard.henderson@linaro.org
>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>> ---
>>  linux-user/elfload.c | 1 +
>>  target/arm/cpu.c     | 7 +++++++
>>  target/arm/cpu64.c   | 1 +
>>  3 files changed, 9 insertions(+)
>>
>> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
>> index 13bc78d0c86..d1231ad07a3 100644
>> --- a/linux-user/elfload.c
>> +++ b/linux-user/elfload.c
>> @@ -584,6 +584,7 @@ static uint32_t get_elf_hwcap(void)
>>      GET_FEATURE(ARM_FEATURE_V8_ATOMICS, ARM_HWCAP_A64_ATOMICS);
>>      GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM);
>>      GET_FEATURE(ARM_FEATURE_V8_FCMA, ARM_HWCAP_A64_FCMA);
>> +    GET_FEATURE(ARM_FEATURE_SVE, ARM_HWCAP_A64_SVE);
>>  #undef GET_FEATURE
>>
>>      return hwcaps;
>> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
>> index 2ae4fffafb9..6dcc552e143 100644
>> --- a/target/arm/cpu.c
>> +++ b/target/arm/cpu.c
>> @@ -164,6 +164,13 @@ static void arm_cpu_reset(CPUState *s)
>>          env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
>>          /* and to the FP/Neon instructions */
>>          env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
>> +        /* and to the SVE instructions */
>> +        env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
>> +        env->cp15.cptr_el[3] |= CPTR_EZ;
>> +        /* with maximum vector length */
>> +        env->vfp.zcr_el[1] = ARM_MAX_VQ - 1;
>> +        env->vfp.zcr_el[2] = ARM_MAX_VQ - 1;
>> +        env->vfp.zcr_el[3] = ARM_MAX_VQ - 1;
>>  #else
>>          /* Reset into the highest available EL */
>>          if (arm_feature(env, ARM_FEATURE_EL3)) {
>> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
>> index c50dcd4077d..0360d7efc5e 100644
>> --- a/target/arm/cpu64.c
>> +++ b/target/arm/cpu64.c
>> @@ -252,6 +252,7 @@ static void aarch64_max_initfn(Object *obj)
>>          set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
>>          set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
>>          set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
>> +        set_feature(&cpu->env, ARM_FEATURE_SVE);
>>          /* For usermode -cpu max we can use a larger and more efficient DCZ
>>           * blocksize since we don't have to follow what the hardware does.
>>           */
>>
>
> Running some tests for my pull request, I've found this commit breaks
> ltp-full-20180515 sigaltstack01 tests with ubuntu arm64/trusty.
>
> sigaltstack01  274  TBROK  :  tst_sig.c:233: unexpected signal
> SIGIOT/SIGABRT(6) received (pid = 15241).
> *** Error in `/opt/ltp/testcases/bin/sigaltstack01': free(): invalid
> pointer: 0x000000000042a010 ***

I wonder if that is the test case not handling the full frame size (or
us not checking the allocated size). What syscall or signal delivery was
happening at the time?

>
> Thanks,
> Laurent


--
Alex Bennée

  reply	other threads:[~2018-11-12 22:13 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-29 14:52 [Qemu-devel] [PULL 00/55] target-arm queue Peter Maydell
2018-06-29 14:52 ` [Qemu-devel] [PULL 01/55] hw/block/fdc: Replace error_setg(&error_abort) by assert() Peter Maydell
2018-06-29 14:52 ` [Qemu-devel] [PULL 02/55] hw/arm/sysbus-fdt: Replace error_setg(&error_fatal) by error_report() + exit() Peter Maydell
2018-06-29 14:52 ` [Qemu-devel] [PULL 03/55] device_tree: " Peter Maydell
2018-06-29 14:52 ` [Qemu-devel] [PULL 04/55] device_tree: Add qemu_fdt_node_unit_path Peter Maydell
2018-06-29 14:52 ` [Qemu-devel] [PULL 05/55] hw/arm/virt: Silence dtc /intc warnings Peter Maydell
2018-06-29 14:52 ` [Qemu-devel] [PULL 06/55] hw/arm/virt: Silence dtc /memory warning Peter Maydell
2018-06-29 14:52 ` [Qemu-devel] [PULL 07/55] target/arm: Implement SVE Memory Contiguous Load Group Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 08/55] target/arm: Implement SVE Contiguous Load, first-fault and no-fault Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 09/55] target/arm: Implement SVE Memory Contiguous Store Group Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 10/55] target/arm: Implement SVE load and broadcast quadword Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 11/55] target/arm: Implement SVE integer convert to floating-point Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 12/55] target/arm: Implement SVE floating-point arithmetic (predicated) Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 13/55] target/arm: Implement SVE FP Multiply-Add Group Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 14/55] target/arm: Implement SVE Floating Point Accumulating Reduction Group Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 15/55] target/arm: Implement SVE load and broadcast element Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 16/55] target/arm: Implement SVE store vector/predicate register Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 17/55] target/arm: Implement SVE scatter stores Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 18/55] target/arm: Implement SVE prefetches Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 19/55] target/arm: Implement SVE gather loads Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 20/55] target/arm: Implement SVE first-fault " Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 21/55] target/arm: Implement SVE scatter store vector immediate Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 22/55] target/arm: Implement SVE floating-point compare vectors Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 23/55] target/arm: Implement SVE floating-point arithmetic with immediate Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 24/55] target/arm: Implement SVE Floating Point Multiply Indexed Group Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 25/55] target/arm: Implement SVE FP Fast Reduction Group Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 26/55] target/arm: Implement SVE Floating Point Unary Operations - Unpredicated Group Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 27/55] target/arm: Implement SVE FP Compare with Zero Group Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 28/55] target/arm: Implement SVE floating-point trig multiply-add coefficient Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 29/55] target/arm: Implement SVE floating-point convert precision Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 30/55] target/arm: Implement SVE floating-point convert to integer Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 31/55] target/arm: Implement SVE floating-point round to integral value Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 32/55] target/arm: Implement SVE floating-point unary operations Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 33/55] target/arm: Implement SVE MOVPRFX Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 34/55] target/arm: Implement SVE floating-point complex add Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 35/55] target/arm: Implement SVE fp complex multiply add Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 36/55] target/arm: Pass index to AdvSIMD FCMLA (indexed) Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 37/55] target/arm: Implement SVE fp complex multiply add (indexed) Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 38/55] target/arm: Implement SVE dot product (vectors) Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 39/55] target/arm: Implement SVE dot product (indexed) Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 40/55] target/arm: Enable SVE for aarch64-linux-user Peter Maydell
2018-11-12 21:10   ` Laurent Vivier
2018-11-12 22:12     ` Alex Bennée [this message]
2018-11-13  9:08       ` Laurent Vivier
2018-11-13  9:49     ` Richard Henderson
2018-11-13  9:57       ` Laurent Vivier
2018-11-13  9:51     ` Richard Henderson
2018-11-13 10:04       ` Laurent Vivier
2018-06-29 14:53 ` [Qemu-devel] [PULL 41/55] target/arm: Implement ARMv8.2-DotProd Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 42/55] target/arm: support reading of CNT[VCT|FRQ]_EL0 from user-space Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 43/55] i.mx7d: Remove unused header files Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 44/55] i.mx7d: Change SRC unimplemented device name from sdma to src Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 45/55] i.mx7d: Change IRQ number type from hwaddr to int Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 46/55] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 47/55] target/arm: Remove redundant DIV detection for KVM Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 48/55] target/arm: Mark PMINTENSET accesses as possibly doing IO Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 49/55] sd: Don't trace SDRequest crc field Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 50/55] sdcard: Use the ldst API Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 51/55] target/arm: Fix SVE signed division vs x86 overflow exception Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 52/55] target/arm: Fix SVE system register access checks Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 53/55] target/arm: Prune a57 features from max Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 54/55] target/arm: Prune a15 " Peter Maydell
2018-06-29 14:53 ` [Qemu-devel] [PULL 55/55] target/arm: Add ID_ISAR6 Peter Maydell
2018-06-30 12:33 ` [Qemu-devel] [PULL 00/55] target-arm queue Peter Maydell

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