From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: Richard Henderson <rth@twiddle.net>,
qemu-ppc@nongnu.org, david@gibson.dropbear.id.au
Cc: qemu-devel@nongnu.org, benh@kernel.crashing.org
Subject: Re: [Qemu-devel] [PATCH 2/4] target-ppc: implement vnegw/d instructions
Date: Mon, 10 Oct 2016 10:42:45 +0530 [thread overview]
Message-ID: <87d1j8948i.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> (raw)
In-Reply-To: <452e40f3-bf23-4e3f-7e44-d663ecae75a2@twiddle.net>
Richard Henderson <rth@twiddle.net> writes:
> On 10/07/2016 01:57 PM, Nikunj A Dadhania wrote:
>> + r->element[i] = (~(b->element[i]) + 1) & mask; \
>
> Any reason you're not writing this as a proper negate?
No particular reason, I was just trying to mimic the pseudo code in the
ISA.
r->element[i] = -b->element[i];
Should be fine as well.
Regards,
Nikunj
next prev parent reply other threads:[~2016-10-10 5:13 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-07 18:56 [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part6 Nikunj A Dadhania
2016-10-07 18:57 ` [Qemu-devel] [PATCH 1/4] target-ppc: implement vexts[bh]2w and vexts[bhw]2d Nikunj A Dadhania
2016-10-09 23:07 ` Richard Henderson
2016-10-10 5:05 ` Nikunj A Dadhania
2016-10-07 18:57 ` [Qemu-devel] [PATCH 2/4] target-ppc: implement vnegw/d instructions Nikunj A Dadhania
2016-10-09 23:09 ` Richard Henderson
2016-10-10 5:12 ` Nikunj A Dadhania [this message]
2016-10-07 18:57 ` [Qemu-devel] [PATCH 3/4] target-ppc: implement xxbr[qdwh] instruction Nikunj A Dadhania
2016-10-10 15:33 ` Richard Henderson
2016-10-10 15:43 ` Nikunj A Dadhania
2016-10-07 18:57 ` [Qemu-devel] [PATCH 4/4] target-ppc: Add xscmp[eq, gt, ge, ne]dp instructions Nikunj A Dadhania
2016-10-10 15:53 ` Richard Henderson
2016-10-10 16:06 ` Nikunj A Dadhania
2016-10-10 16:18 ` [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part6 no-reply
2016-10-12 4:59 ` Nikunj A Dadhania
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