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Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 Subject: Re: [PULL 00/23] riscv-to-apply queue Content-Language: en-US To: Alistair Francis , qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alistair Francis References: <20220524224428.552334-1-alistair.francis@opensource.wdc.com> From: Richard Henderson In-Reply-To: <20220524224428.552334-1-alistair.francis@opensource.wdc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/24/22 15:44, Alistair Francis wrote: > From: Alistair Francis > > The following changes since commit 3757b0d08b399c609954cf57f273b1167e5d7a8d: > > Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into staging (2022-05-20 08:04:30 -0700) > > are available in the Git repository at: > > git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220525 > > for you to fetch changes up to 8fe63fe8e512d77583d6798acd2164f1fa1e40ab: > > hw/core: loader: Set is_linux to true for VxWorks uImage (2022-05-24 10:38:50 +1000) > > ---------------------------------------------------------------- > Third RISC-V PR for QEMU 7.1 > > * Fixes for accessing VS hypervisor CSRs > * Improvements for RISC-V Vector extension > * Fixes for accessing mtimecmp > * Add new short-isa-string CPU option > * Improvements to RISC-V machine error handling > * Disable the "G" extension by default internally, no functional change > * Enforce floating point extension requirements > * Cleanup ISA extension checks > * Resolve redundant property accessors > * Fix typo of mimpid cpu option > * Improvements for virtulisation > * Add zicsr/zifencei to isa_string > * Support for VxWorks uImage Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate. r~ > > ---------------------------------------------------------------- > Anup Patel (4): > target/riscv: Fix csr number based privilege checking > target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode > target/riscv: Set [m|s]tval for both illegal and virtual instruction traps > hw/riscv: virt: Fix interrupt parent for dynamic platform devices > > Atish Patra (1): > hw/intc: Pass correct hartid while updating mtimecmp > > Bernhard Beschow (2): > hw/vfio/pci-quirks: Resolve redundant property getters > hw/riscv/sifive_u: Resolve redundant property accessors > > Bin Meng (2): > hw/core: Sync uboot_image.h from U-Boot v2022.01 > hw/core: loader: Set is_linux to true for VxWorks uImage > > Dylan Reid (1): > target/riscv: Fix VS mode hypervisor CSR access > > Frank Chang (1): > target/riscv: Fix typo of mimpid cpu option > > Hongren (Zenithal) Zheng (1): > target/riscv: add zicsr/zifencei to isa_string > > Tsukasa OI (9): > target/riscv: Move Zhinx* extensions on ISA string > target/riscv: Add short-isa-string option > hw/riscv: Make CPU config error handling generous (virt/spike) > hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan) > target/riscv: Fix coding style on "G" expansion > target/riscv: Disable "G" by default > target/riscv: Change "G" expansion > target/riscv: FP extension requirements > target/riscv: Move/refactor ISA extension checks > > Weiwei Li (1): > target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize > > eopXD (1): > target/riscv: rvv: Fix early exit condition for whole register load/store > > hw/core/uboot_image.h | 213 +++++++++++++++++++++----------- > target/riscv/cpu.h | 12 +- > hw/core/loader.c | 15 +++ > hw/intc/riscv_aclint.c | 3 +- > hw/riscv/opentitan.c | 2 +- > hw/riscv/sifive_e.c | 2 +- > hw/riscv/sifive_u.c | 28 +---- > hw/riscv/spike.c | 2 +- > hw/riscv/virt.c | 27 ++-- > hw/vfio/pci-quirks.c | 34 ++--- > target/riscv/cpu.c | 91 ++++++++++---- > target/riscv/cpu_helper.c | 4 +- > target/riscv/csr.c | 26 ++-- > target/riscv/translate.c | 17 ++- > target/riscv/insn_trans/trans_rvv.c.inc | 58 +++++---- > 15 files changed, 325 insertions(+), 209 deletions(-) >