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Mon, 01 Apr 2024 22:56:39 +0200 From: Sven Schnelle To: Richard Henderson Cc: qemu-devel@nongnu.org, Helge Deller Subject: Re: [PATCH] target/hppa: mask upper iaoq bits when returning to narrow mode In-Reply-To: <87il10zu46.fsf@t14.stackframe.org> (Sven Schnelle's message of "Mon, 01 Apr 2024 22:49:13 +0200") References: <20240401145201.2175873-1-svens@stackframe.org> <0f5697e6-da79-424b-866d-40d11b4db0bb@linaro.org> <87msqczujz.fsf@t14.stackframe.org> <87il10zu46.fsf@t14.stackframe.org> Date: Mon, 01 Apr 2024 22:56:38 +0200 Message-ID: <87edboztrt.fsf@t14.stackframe.org> MIME-Version: 1.0 Content-Type: text/plain Received-SPF: pass client-ip=23.83.216.32; envelope-from=svens@stackframe.org; helo=catfish.pear.relay.mailchannels.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sven Schnelle writes: > Sven Schnelle writes: > >> Richard Henderson writes: >> >>> On 4/1/24 04:52, Sven Schnelle wrote: >>>> For unknown reasons, Java 1.5 on 64-bit HP-UX 11.11 does signed >>>> computation of the new IAOQ value in the signal handler. In the >>>> current code these bits are not masked when returning to narrow >>>> mode, causing java to crash. >>>> Signed-off-by: Sven Schnelle >>>> --- >>>> target/hppa/sys_helper.c | 4 ++++ >>>> 1 file changed, 4 insertions(+) >>>> diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c >>>> index 208e51c086..3bbc2da71b 100644 >>>> --- a/target/hppa/sys_helper.c >>>> +++ b/target/hppa/sys_helper.c >>>> @@ -83,6 +83,10 @@ void HELPER(rfi)(CPUHPPAState *env) >>>> env->iaoq_f = env->cr[CR_IIAOQ]; >>>> env->iaoq_b = env->cr_back[1]; >>>> + if (!(env->cr[CR_IPSW] & PSW_W)) { >>>> + env->iaoq_f &= 0xffffffff; >>>> + env->iaoq_b &= 0xffffffff; >>>> + } >>> >>> This shouldn't be needed, because we are already masking these bits >>> later, in cpu_get_tb_cpu_state. But I do have some cleanups in this >>> area, and perhaps one of them matters. >> Any thoughts? Otherwise i need to investigate and make a wrong patch >> again :-) > > This seems to be caused by IIAOQ's containing the upper bits. With the > patch below i'm able to boot. Not sure whether it's correct though. > > diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c > index 58c13d3e61..f7c4cca8f1 100644 > --- a/target/hppa/int_helper.c > +++ b/target/hppa/int_helper.c > @@ -123,8 +123,14 @@ void hppa_cpu_do_interrupt(CPUState *cs) > env->cr[CR_IIASQ] = 0; > env->cr_back[0] = 0; > } > - env->cr[CR_IIAOQ] = env->iaoq_f; > - env->cr_back[1] = env->iaoq_b; > + if (old_psw & PSW_W) { > + env->cr[CR_IIAOQ] = env->iaoq_f; > + env->cr_back[1] = env->iaoq_b; > + } else { > + env->cr[CR_IIAOQ] = (env->iaoq_f & 0xffffffff); > + env->cr_back[1] = env->iaoq_b & 0xffffffff; > + } > + I guess the interesting question where should these bits get masked out - i would assume that this place is to late, and it should happen earlier in trans_be/when the iaoq value is copied. On the other hand you had one commit that removed the masking in copy_iaoq_entry()...