How to synchronize CPUs on MMIO read?

How to synchronize CPUs on MMIO read?

[Igor Lesik]

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Hi.
I need to model some custom HW that synchronizes CPUs when they read MMIO register N: MMIO read does not return until another CPU writes to MMIO register M. I modeled this behavior with a) on MMIO read of N, save CPU into a list of waiting CPUs and put it asleep with cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT) and b) on MMIO write to M, wake all waiting CPUs with cpu->halted = 0; qemu_cpu_kick(cpu). It seems to work fine. However, this HW has a twist: MMIO read of N returns a value that was written by MMIO write to M. Can anyone please advise how this could be done?

Thanks!
Igor

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Re: How to synchronize CPUs on MMIO read?

[Alex Bennée]

Igor Lesik <lesikigor@meta.com> writes:

> Hi.
>
> I need to model some custom HW that synchronizes CPUs when they read MMIO register N: MMIO read does not
> return until another CPU writes to MMIO register M. I modeled this behavior with a) on MMIO read of N, save CPU into
> a list of waiting CPUs and put it asleep with cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT) and b) on MMIO write
> to M, wake all waiting CPUs with cpu->halted = 0; qemu_cpu_kick(cpu). It seems to work fine. However, this HW has a
> twist: MMIO read of N returns a value that was written by MMIO write to M. Can anyone please advise how this could
> be done?

Under TCG all MMIO accesses should be serialised by the BQL so no other
MMIO access can be taking place until you finish the operation.

>
>  
>
> Thanks!
>
> Igor


-- 
Alex Bennée
Virtualisation Tech Lead @ Linaro

Re: How to synchronize CPUs on MMIO read?

[Richard Henderson]

On 8/16/23 09:31, Igor Lesik wrote:
> Hi.
> 
> I need to model some custom HW that synchronizes CPUs when they read MMIO register N: MMIO 
> read does not return until another CPU writes to MMIO register M. I modeled this behavior 
> with a) on MMIO read of N, save CPU into a list of waiting CPUs and put it asleep with 
> cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT) and b) on MMIO write to M, wake all waiting 
> CPUs with cpu->halted = 0; qemu_cpu_kick(cpu). It seems to work fine. However, this HW has 
> a twist: MMIO read of N returns a value that was written by MMIO write to M. Can anyone 
> please advise how this could be done?

You'll want to add something to allow each cpu to latch the value written.

Something like

     CPU_FOREACH(cpu) {
         if (cpu != write_cpu) {
             *cpu->mmio_latch = value;
             qemu_cpu_kick(cpu);
         }
     }

where cpu->sync_latch = &cpu->env.reg[N] for the register destination of the MMIO read.

This is easy if you can identify the hw sync mmio during translation.  If this sync is 
mapped somewhere arbitrary within the address space, you may have to work harder.



r~