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Tue, 21 Jun 2022 21:26:32 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 69F77AC05F; Tue, 21 Jun 2022 21:26:31 +0000 (GMT) Received: from localhost (unknown [9.160.71.76]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTPS; Tue, 21 Jun 2022 21:26:31 +0000 (GMT) From: Fabiano Rosas To: Leandro Lupori , qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, Leandro Lupori Subject: Re: [PATCH 3/3] target/ppc: Check page dir/table base alignment In-Reply-To: <20220620202704.78978-4-leandro.lupori@eldorado.org.br> References: <20220620202704.78978-1-leandro.lupori@eldorado.org.br> <20220620202704.78978-4-leandro.lupori@eldorado.org.br> Date: Tue, 21 Jun 2022 18:26:29 -0300 Message-ID: <87edzhaet6.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: YA_FEyefTLFDDQo_sLldS0wJFFKor7LQ X-Proofpoint-GUID: 6IjBFHf5y8thB5opnKK-SQ7YjuLDyhE4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-21_09,2022-06-21_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 suspectscore=0 impostorscore=0 clxscore=1015 spamscore=0 malwarescore=0 mlxscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206210089 Received-SPF: pass client-ip=148.163.158.5; envelope-from=farosas@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Leandro Lupori writes: > Check if each page dir/table base address is properly aligned and > log a guest error if not, as real hardware behave incorrectly in > this case. > > These checks are only performed when DEBUG_MMU is defined, to avoid > hurting the performance. > > Signed-off-by: Leandro Lupori > --- > target/ppc/mmu-radix64.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c > index 2f0bcbfe2e..80d945a7c3 100644 > --- a/target/ppc/mmu-radix64.c > +++ b/target/ppc/mmu-radix64.c > @@ -28,6 +28,8 @@ > #include "mmu-radix64.h" > #include "mmu-book3s-v3.h" > > +/* #define DEBUG_MMU */ > + > static bool ppc_radix64_get_fully_qualified_addr(const CPUPPCState *env, > vaddr eaddr, > uint64_t *lpid, uint64_t *pid) > @@ -277,6 +279,16 @@ static int ppc_radix64_next_level(AddressSpace *as, vaddr eaddr, > if (!(pde & R_PTE_LEAF)) { /* Prepare for next iteration */ > ++*level; > *nls = pde & R_PDE_NLS; > + > +#ifdef DEBUG_MMU > + if ((pde & R_PDE_NLB) & MAKE_64BIT_MASK(0, *nls + 3)) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: misaligned page dir/table base: 0x%"VADDR_PRIx > + " page dir size: 0x%"PRIx64" level: %d\n", > + __func__, (pde & R_PDE_NLB), BIT(*nls + 3), *level); > + } > +#endif Maybe use qemu_log_enabled() instead of the define? I think it is a little more useful and has less chance to rot. > + > index = eaddr >> (*psize - *nls); /* Shift */ > index &= ((1UL << *nls) - 1); /* Mask */ > *pte_addr = (pde & R_PDE_NLB) + (index * sizeof(pde)); > @@ -297,6 +309,15 @@ static int ppc_radix64_walk_tree(AddressSpace *as, vaddr eaddr, > return 1; > } > > +#ifdef DEBUG_MMU > + if (base_addr & MAKE_64BIT_MASK(0, nls + 3)) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: misaligned page dir base: 0x%"VADDR_PRIx > + " page dir size: 0x%"PRIx64"\n", > + __func__, base_addr, BIT(nls + 3)); > + } > +#endif > + > index = eaddr >> (*psize - nls); /* Shift */ > index &= ((1UL << nls) - 1); /* Mask */ > *pte_addr = base_addr + (index * sizeof(pde));