From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
Pranith Kumar <bobby.prani@gmail.com>
Subject: Re: [Qemu-devel] ARM v6 memory barrier cp15 ops still implemented as NOPs
Date: Fri, 16 Jun 2017 20:41:03 +0100 [thread overview]
Message-ID: <87efujbu0g.fsf@linaro.org> (raw)
In-Reply-To: <CAFEAcA8ZTj4YRdcnSdMw6fEizEKa-cJndZG+=WFkkMDKHX9mYw@mail.gmail.com>
Peter Maydell <peter.maydell@linaro.org> writes:
> Hi; I just noticed that we seem to still implement the ARM v6
> memory-barrier cp15 ops as NOPs:
>
> { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
> .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
> { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
> .access = PL0_W, .type = ARM_CP_NOP },
> { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
> .access = PL0_W, .type = ARM_CP_NOP },
>
> Don't these need to do something more complicated with the
> advent of MTTCG ?
Yeah they should - what does ISB do that it needs a write handler?
>
> thanks
> -- PMM
--
Alex Bennée
next prev parent reply other threads:[~2017-06-16 19:40 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-16 17:34 [Qemu-devel] ARM v6 memory barrier cp15 ops still implemented as NOPs Peter Maydell
2017-06-16 19:41 ` Alex Bennée [this message]
2017-06-18 18:23 ` Peter Maydell
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