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From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
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Date: Fri, 16 Jun 2017 20:41:03 +0100
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Subject: Re: [Qemu-devel] ARM v6 memory barrier cp15 ops still implemented
 as NOPs
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>, Pranith Kumar <bobby.prani@gmail.com>


Peter Maydell <peter.maydell@linaro.org> writes:

> Hi; I just noticed that we seem to still implement the ARM v6
> memory-barrier cp15 ops as NOPs:
>
>     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
>       .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
>     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
>       .access = PL0_W, .type = ARM_CP_NOP },
>     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
>       .access = PL0_W, .type = ARM_CP_NOP },
>
> Don't these need to do something more complicated with the
> advent of MTTCG ?

Yeah they should - what does ISB do that it needs a write handler?

>
> thanks
> -- PMM


--
Alex Bennée