* [Qemu-devel] ARM v6 memory barrier cp15 ops still implemented as NOPs
@ 2017-06-16 17:34 Peter Maydell
2017-06-16 19:41 ` Alex Bennée
0 siblings, 1 reply; 3+ messages in thread
From: Peter Maydell @ 2017-06-16 17:34 UTC (permalink / raw)
To: QEMU Developers; +Cc: Alex Bennée
Hi; I just noticed that we seem to still implement the ARM v6
memory-barrier cp15 ops as NOPs:
{ .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
.access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
{ .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
.access = PL0_W, .type = ARM_CP_NOP },
{ .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
.access = PL0_W, .type = ARM_CP_NOP },
Don't these need to do something more complicated with the
advent of MTTCG ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [Qemu-devel] ARM v6 memory barrier cp15 ops still implemented as NOPs
2017-06-16 17:34 [Qemu-devel] ARM v6 memory barrier cp15 ops still implemented as NOPs Peter Maydell
@ 2017-06-16 19:41 ` Alex Bennée
2017-06-18 18:23 ` Peter Maydell
0 siblings, 1 reply; 3+ messages in thread
From: Alex Bennée @ 2017-06-16 19:41 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, Pranith Kumar
Peter Maydell <peter.maydell@linaro.org> writes:
> Hi; I just noticed that we seem to still implement the ARM v6
> memory-barrier cp15 ops as NOPs:
>
> { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
> .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
> { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
> .access = PL0_W, .type = ARM_CP_NOP },
> { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
> .access = PL0_W, .type = ARM_CP_NOP },
>
> Don't these need to do something more complicated with the
> advent of MTTCG ?
Yeah they should - what does ISB do that it needs a write handler?
>
> thanks
> -- PMM
--
Alex Bennée
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [Qemu-devel] ARM v6 memory barrier cp15 ops still implemented as NOPs
2017-06-16 19:41 ` Alex Bennée
@ 2017-06-18 18:23 ` Peter Maydell
0 siblings, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2017-06-18 18:23 UTC (permalink / raw)
To: Alex Bennée; +Cc: QEMU Developers, Pranith Kumar
On 16 June 2017 at 20:41, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Peter Maydell <peter.maydell@linaro.org> writes:
>
>> Hi; I just noticed that we seem to still implement the ARM v6
>> memory-barrier cp15 ops as NOPs:
>>
>> { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
>> .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
>> { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
>> .access = PL0_W, .type = ARM_CP_NOP },
>> { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
>> .access = PL0_W, .type = ARM_CP_NOP },
>>
>> Don't these need to do something more complicated with the
>> advent of MTTCG ?
>
> Yeah they should - what does ISB do that it needs a write handler?
The comment just above the ISB definition says:
/* We need to break the TB after ISB to execute self-modifying code
* correctly and also to take any pending interrupts immediately.
* So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
*/
thanks
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
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2017-06-16 17:34 [Qemu-devel] ARM v6 memory barrier cp15 ops still implemented as NOPs Peter Maydell
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