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Mon, 24 Nov 2025 07:01:04 -0800 (PST) Received: from draig.lan ([185.126.160.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477bf3af0ecsm202300355e9.9.2025.11.24.07.01.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 07:01:04 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 5C04A5F83A; Mon, 24 Nov 2025 15:01:03 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Jim MacArthur Cc: qemu-devel@nongnu.org Subject: Re: [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits In-Reply-To: <20251120125833.123813-4-jim.macarthur@linaro.org> (Jim MacArthur's message of "Thu, 20 Nov 2025 12:54:16 +0000") References: <20251120125833.123813-1-jim.macarthur@linaro.org> <20251120125833.123813-4-jim.macarthur@linaro.org> User-Agent: mu4e 1.12.14-pre3; emacs 30.1 Date: Mon, 24 Nov 2025 15:01:03 +0000 Message-ID: <87fra38ogg.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Jim MacArthur writes: > Tests ASID2 is present and FNG1, FNG0, and A2 are writable, and read > value shows the update. > > Signed-off-by: Jim MacArthur > --- > tests/tcg/aarch64/system/asid2.c | 53 ++++++++++++++++++++++++++++++++ > 1 file changed, 53 insertions(+) > create mode 100644 tests/tcg/aarch64/system/asid2.c > > diff --git a/tests/tcg/aarch64/system/asid2.c b/tests/tcg/aarch64/system/= asid2.c > new file mode 100644 > index 0000000000..cfe69db2ae > --- /dev/null > +++ b/tests/tcg/aarch64/system/asid2.c > @@ -0,0 +1,53 @@ > +/* > + * ASID2 Feature presence and enabled TCR2_EL1 bits test > + * > + * Copyright (c) 2025 Linaro Ltd > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include > +#include > + > +#define ID_AA64MMFR4_EL1 "S3_0_C0_C7_4" > +#define TCR2_EL1 "S3_0_C2_C0_3" > + > +int main() > +{ > + /* > + * Test for presence of ASID2 and three feature bits enabled by it: > + * https://developer.arm.com/documentation/109697/2025_09/Feature-de= scriptions/The-Armv9-5-architecture-extension > + * Bits added are FNG1, FNG0, and A2. These should be RES0 if A2 is > + * not enabled and read as the written value if A2 is enabled. > + */ > + > + uint64_t out; > + uint64_t idreg; > + > + /* Mask is FNG1, FNG0, and A2 */ > + const uint64_t feature_mask =3D (1ULL << 18 | 1ULL << 17 | 1ULL << 1= 6); > + const uint64_t in =3D feature_mask; > + > + asm("mrs %[x1], " ID_AA64MMFR4_EL1 "\n\t" > + : [x1] "=3Dr" (idreg)); > + if ((idreg & 0xF00) !=3D 0) { > + /* ASID2 is enabled */ > + } else { > + ml_printf("FAIL: ASID2 not present in ID_AA64MMFR4 (%lx)\n", idr= eg); > + return 1; > + } If we instead use this to test for the presence of the feature and then... > + > + asm("msr " TCR2_EL1 ", %[x0]\n\t" > + "mrs %[x1], " TCR2_EL1 "\n\t" > + : [x1] "=3Dr" (out) > + : [x0] "r" (in)); > + > + if ((out & feature_mask) =3D=3D in) { > + ml_printf("OK\n"); > + return 0; > + } else { > + ml_printf("FAIL: read value %lx !=3D written value %lx\n", > + out & feature_mask, in); > + return 1; > + } extend this part to check the bits are behaving as the feature dictates then we can add a second test like this (Makefile.softmmu-target): run-asid2-oldcpu: asid2 $(call run-test, $<, \ $(QEMU) -monitor none -display none \ -chardev file$(COMMA)path=3D$<.out$(COMMA)id=3Doutput \ $(QEMU_OPTS) $<) run-asid2-oldcpu: QEMU_OPTS=3D-M virt -cpu cortex-a72 -display none $(QEM= U_BASE_ARGS) -kernel EXTRA_RUNS +=3D run-asid2-oldcpu Although its a bit clunky - one day I'll get around to converting this lot to meson. > +} --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro