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Fri, 29 Nov 2024 15:51:20 +0000 (UTC) Received: from localhost (dhcp-192-244.str.redhat.com [10.33.192.244]) by mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 16249195605A; Fri, 29 Nov 2024 15:51:17 +0000 (UTC) From: Cornelia Huck To: Peter Maydell Cc: eric.auger@redhat.com, =?utf-8?Q?Daniel_P=2E_Berrang=C3=A9?= , eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, abologna@redhat.com, jdenemar@redhat.com, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: Re: [RFC 18/21] arm/cpu: Introduce a customizable kvm host cpu model In-Reply-To: Organization: "Red Hat GmbH, Sitz: Werner-von-Siemens-Ring 12, D-85630 Grasbrunn, Handelsregister: Amtsgericht =?utf-8?Q?M=C3=BCnchen=2C?= HRB 153243, =?utf-8?Q?Gesch=C3=A4ftsf=C3=BChrer=3A?= Ryan Barnhart, Charles Cachera, Michael O'Neill, Amy Ross" References: <20241025101959.601048-1-eric.auger@redhat.com> <20241025101959.601048-19-eric.auger@redhat.com> <63c232c2-a325-48d6-8ed4-753a7c6e3b4e@redhat.com> <87ikstn8sc.fsf@redhat.com> <87frnwmn2v.fsf@redhat.com> <87ldx2krdp.fsf@redhat.com> User-Agent: Notmuch/0.38.3 (https://notmuchmail.org) Date: Fri, 29 Nov 2024 16:51:15 +0100 Message-ID: <87frnakpho.fsf@redhat.com> MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass client-ip=170.10.133.124; envelope-from=cohuck@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Nov 29 2024, Peter Maydell wrote: > On Fri, 29 Nov 2024 at 15:10, Cornelia Huck wrote: >> The good news is that in many cases we only have differences in bits >> that map to a feature (and are actually writable in current KVM.) The >> bad news is that we have a number of exceptions. >> >> Comparison #1: >> >> ID_AA64DFR0 >> f010307009 #of breakpoints:7 >> f010305009 #of breakpoints:5 >> >> BRPs does not match to any feature (but has a different meaning when we >> have FEAT_Debugv8p9 and 16+ breakpoints) >> [this is a whole can of worms in general] >> >> ID_AA64MMFR0 >> 2100022200101026 FEAT_ECV, FEAT_FGT, 4PB >> 0000022200101125 mixed endian, 256TB >> >> FEAT_ECV -> may be 1 or 2 in ECV, with different capabilities (I guess >> we would need to allow something like FEAT_ECV=2 to expess this?) > > This one was an unfortunate oversight; I expect that there > will be a separate feature name for the =2 case in some future > spec release. But as you note for FEAT_BBM below, not > every different ID field value always has its own FEAT_ name. > (FEAT_HAFDBS is another -- it allows ID_AA64MMFR1_EL1.HAFDBS to > be 1 or 2.) Ah yes, I actually noticed FEAT_HAFDBS as well. > >> support for mixed endian -> indicated in BigEnd, no feature (how >> relevant is this in practice?) > > ID_AA64MMFR0_EL1.BigEnd == 1 is FEAT_MixedEnd. Relevant if your > guest or its userspace wants to use big-endian, which is probably > approximately nobody in a KVM context but is theoretically possible. Ok, that one I missed in the list; if there's a feature, we should be able to use it. > >> PARange (52 bits/4PB vs 48 bits/256TB) -> no feature, but some values >> depend on other features -- we care about this when creating a cpu, but >> migrating to another system with a mismatched range would be >> problematic, unless configuration outside of the cpu model would take >> care of it >> >> Comparison #2: >> >> ID_AA64PFR0 >> 1101011021111111 FEAT_AMUv1, GIC v3.0/4.0 >> 1101001020111111 >> >> GIC == 1 indicates GIC CPU sysreg interface for 3.0/4.0, but no feature >> (I'm not quite sure how we handle this in QEMU) > > We basically defer GIC emulation almost entirely to the > kernel (which will set the GIC bit in the ID registers > according to whether userspace asked it for a GIC or not). > >> ID_AA64MMFR1 >> 1000000010312122 FEAT_ECBHB, !FEAT_ETS2, FEAT_PAN3, FEAT_HPDS2, FEAT_HAFDBS >> 0000001010211120 !FEAT_ETS2, FEAT_PAN2, FEAT_HPDS >> >> both ETS == 0 and ETS == 1 indicate that FEAT_ETS2 is not implememented >> (ETS == 2 would indicate FEAT_ETS2) -- I guess we would want to >> standardize on ETS == 0 >> FEAT_PAN3 implies FEAT_PAN2, and FEAT_HPDS2 implies FEAT_HPDS2, so >> probably fine > > Yes, in general if the number in the field gets bigger > this should be a backwards-compatible improvement in > the feature. Indeed, I hope that this will be the case for new features.