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Tue, 4 Jan 2022 20:51:30 +0000 (GMT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 85B5E78074; Tue, 4 Jan 2022 20:51:29 +0000 (GMT) Received: from localhost (unknown [9.163.4.248]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTPS; Tue, 4 Jan 2022 20:51:29 +0000 (GMT) From: Fabiano Rosas To: qemu-devel@nongnu.org Subject: Re: [PATCH 6/9] target/ppc: powerpc_excp: Preserve MSR_LE bit In-Reply-To: <20220103220746.3916246-7-farosas@linux.ibm.com> References: <20220103220746.3916246-1-farosas@linux.ibm.com> <20220103220746.3916246-7-farosas@linux.ibm.com> Date: Tue, 04 Jan 2022 17:51:27 -0300 Message-ID: <87fsq3ns1c.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: W5ku9CrUuyneDdeSZ0CKjET5pLWF_vHB X-Proofpoint-ORIG-GUID: D-131QxTs27woGGZk2eGecx-YFZerVbJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-04_10,2022-01-04_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 impostorscore=0 suspectscore=0 phishscore=0 mlxscore=0 mlxlogscore=578 spamscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201040133 Received-SPF: pass client-ip=148.163.158.5; envelope-from=farosas@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: 0 X-Spam_score: -0.1 X-Spam_bar: / X-Spam_report: (-0.1 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, richard.henderson@linaro.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Fabiano Rosas writes: > We currently clear MSR_LE when copying bits from env->msr to > new_msr. However, for CPUs that do not have LPCR_ILE we always set > new_msr[LE] according to env->msr[LE]. And for CPUs that do have ILE > support we need to check LPCR/HID0 anyway, so there's no need to clear > the bit when copying. > > Signed-off-by: Fabiano Rosas > --- > target/ppc/excp_helper.c | 14 +++++--------- > 1 file changed, 5 insertions(+), 9 deletions(-) > > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > index 5d31940426..e56ddbe5d5 100644 > --- a/target/ppc/excp_helper.c > +++ b/target/ppc/excp_helper.c > @@ -348,10 +348,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp) > } > > /* > - * new interrupt handler msr preserves existing HV and ME unless > - * explicitly overriden > + * new interrupt handler msr preserves existing HV, ME and LE > + * unless explicitly overriden. > */ > - new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); > + new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB | MSR_LE); > > /* target registers */ > srr0 = SPR_SRR0; > @@ -763,13 +763,9 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp) > if (excp_model >= POWERPC_EXCP_970) { > if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { > new_msr |= (target_ulong)1 << MSR_LE; > + } else { > + new_msr &= ~((target_ulong)1 << MSR_LE); > } > - } else if (msr_ile) { > - new_msr |= (target_ulong)1 << MSR_LE; > - } > -#else > - if (msr_ile) { > - new_msr |= (target_ulong)1 << MSR_LE; > } > #endif This patch is incorrect, don't bother with it. I misread the msr_ile macro as msr_le. I'll think of an alternative.