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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Peter Maydell writes: > Architecturally, Neon FP16 operations use the "standard FPSCR" like > all other Neon operations. However, this is defined in the Arm ARM > pseudocode as "a fixed value, except that FZ16 (and AHP) follow the > FPSCR bits". In QEMU, the softfloat float_status doesn't include > separate flush-to-zero for FP16 operations, so we must keep separate > fp_status for "Neon non-FP16" and "Neon fp16" operations, in the > same way we do already for the non-Neon "fp_status" vs "fp_status_f16". > > Add the extra float_status field to the CPU state structure, > ensure it is correctly initialized and updated on FPSCR writes, > and make fpstatus_ptr(FPST_STD_F16) return a pointer to it. > > Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e