Re: [PATCH 2/3] target/arm: Use tcg_gen_gvec_mov for clear_vec_high

["Alex Bennée" <alex.bennee@linaro.org>]

Richard Henderson <richard.henderson@linaro.org> writes:

> The 8-byte store for the end a !is_q operation can be
> merged with the other stores.  Use a no-op vector move
> to trigger the expand_clr portion of tcg_gen_gvec_mov.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  target/arm/translate-a64.c | 10 ++--------
>  1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 095638e09a..d57aa54d6a 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -513,14 +513,8 @@ static void clear_vec_high(DisasContext *s, bool is_q, int rd)
>      unsigned ofs = fp_reg_offset(s, rd, MO_64);
>      unsigned vsz = vec_full_reg_size(s);
>  
> -    if (!is_q) {
> -        TCGv_i64 tcg_zero = tcg_const_i64(0);
> -        tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8);
> -        tcg_temp_free_i64(tcg_zero);
> -    }
> -    if (vsz > 16) {
> -        tcg_gen_gvec_dup_imm(MO_64, ofs + 16, vsz - 16, vsz - 16, 0);
> -    }
> +    /* Nop move, with side effect of clearing the tail. */
> +    tcg_gen_gvec_mov(MO_64, ofs, ofs, is_q ? 16 : 8, vsz);
>  }
>  
>  void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)


-- 
Alex Bennée