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Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > The 8-byte store for the end a !is_q operation can be > merged with the other stores. Use a no-op vector move > to trigger the expand_clr portion of tcg_gen_gvec_mov. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e > --- > target/arm/translate-a64.c | 10 ++-------- > 1 file changed, 2 insertions(+), 8 deletions(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 095638e09a..d57aa54d6a 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -513,14 +513,8 @@ static void clear_vec_high(DisasContext *s, bool is_= q, int rd) > unsigned ofs =3D fp_reg_offset(s, rd, MO_64); > unsigned vsz =3D vec_full_reg_size(s); >=20=20 > - if (!is_q) { > - TCGv_i64 tcg_zero =3D tcg_const_i64(0); > - tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8); > - tcg_temp_free_i64(tcg_zero); > - } > - if (vsz > 16) { > - tcg_gen_gvec_dup_imm(MO_64, ofs + 16, vsz - 16, vsz - 16, 0); > - } > + /* Nop move, with side effect of clearing the tail. */ > + tcg_gen_gvec_mov(MO_64, ofs, ofs, is_q ? 16 : 8, vsz); > } >=20=20 > void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) --=20 Alex Benn=C3=A9e