From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58516) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9qJa-0004cm-NL for qemu-devel@nongnu.org; Mon, 06 Jun 2016 04:55:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b9qJW-0004PB-H1 for qemu-devel@nongnu.org; Mon, 06 Jun 2016 04:55:17 -0400 Received: from mail-wm0-x229.google.com ([2a00:1450:400c:c09::229]:34596) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9qJW-0004P1-9g for qemu-devel@nongnu.org; Mon, 06 Jun 2016 04:55:14 -0400 Received: by mail-wm0-x229.google.com with SMTP id k184so2678351wme.1 for ; Mon, 06 Jun 2016 01:55:14 -0700 (PDT) From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <5754594A.10304@gmail.com> Date: Mon, 06 Jun 2016 09:55:26 +0100 Message-ID: <87fusqitmp.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [RFC v1 10/12] arm: use tlb_flush_page_all for tlbimva[a] List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sergey Fedorov Cc: mttcg@listserver.greensocs.com, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, qemu-devel@nongnu.org, mark.burton@greensocs.com, pbonzini@redhat.com, jan.kiszka@siemens.com, rth@twiddle.net, peter.maydell@linaro.org, claudio.fontana@huawei.com, Peter Crosthwaite , "open list:ARM" Sergey Fedorov writes: > On 15/04/16 17:23, Alex Bennée wrote: >> From: KONRAD Frederic >> >> Instead of flushing each individual vCPU use the tlb_flush_page_all >> functions which is async enabled for MTTCG. >> >> Signed-off-by: KONRAD Frederic >> Signed-off-by: Alex Bennée >> --- >> include/exec/exec-all.h | 3 +++ >> target-arm/helper.c | 12 ++---------- >> 2 files changed, 5 insertions(+), 10 deletions(-) >> >> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h >> index 858055b..bc97683 100644 >> --- a/include/exec/exec-all.h >> +++ b/include/exec/exec-all.h >> @@ -208,6 +208,9 @@ static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, >> static inline void tlb_flush_by_mmuidx(CPUState *cpu, ...) >> { >> } >> +static inline void tlb_flush_page_all(target_ulong addr) >> +{ >> +} > > This change belongs to the patch which introduced the function. Thanks, will fix. > > Kind regards, > Sergey > >> #endif >> >> #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ >> diff --git a/target-arm/helper.c b/target-arm/helper.c >> index 19d5d52..bc9fbda 100644 >> --- a/target-arm/helper.c >> +++ b/target-arm/helper.c >> @@ -554,21 +554,13 @@ static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, >> static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, >> uint64_t value) >> { >> - CPUState *other_cs; >> - >> - CPU_FOREACH(other_cs) { >> - tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); >> - } >> + tlb_flush_page_all(value & TARGET_PAGE_MASK); >> } >> >> static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, >> uint64_t value) >> { >> - CPUState *other_cs; >> - >> - CPU_FOREACH(other_cs) { >> - tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); >> - } >> + tlb_flush_page_all(value & TARGET_PAGE_MASK); >> } >> >> static const ARMCPRegInfo cp_reginfo[] = { -- Alex Bennée