From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40700) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZrovM-00013d-0s for qemu-devel@nongnu.org; Thu, 29 Oct 2015 11:15:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZrovH-0004xm-Uf for qemu-devel@nongnu.org; Thu, 29 Oct 2015 11:15:31 -0400 Received: from mail-wi0-x22a.google.com ([2a00:1450:400c:c05::22a]:38763) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZrovH-0004xg-Lv for qemu-devel@nongnu.org; Thu, 29 Oct 2015 11:15:27 -0400 Received: by wicll6 with SMTP id ll6so45622607wic.1 for ; Thu, 29 Oct 2015 08:15:27 -0700 (PDT) References: <1445883178-576-1-git-send-email-peter.maydell@linaro.org> <1445883178-576-3-git-send-email-peter.maydell@linaro.org> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1445883178-576-3-git-send-email-peter.maydell@linaro.org> Date: Thu, 29 Oct 2015 15:15:25 +0000 Message-ID: <87fv0twvsi.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH for-2.5 2/2] target-arm: Report S/NS status in the CPU debug logs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: "Edgar E. Iglesias" , qemu-devel@nongnu.org, patches@linaro.org Peter Maydell writes: > If this CPU supports EL3, enhance the printing of the current > CPU mode in debug logging to distinguish S from NS modes as > appropriate. > > Signed-off-by: Peter Maydell > --- > target-arm/translate-a64.c | 11 ++++++++++- > target-arm/translate.c | 12 +++++++++++- > 2 files changed, 21 insertions(+), 2 deletions(-) > > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c > index ccefa7b..8ebdcb7 100644 > --- a/target-arm/translate-a64.c > +++ b/target-arm/translate-a64.c > @@ -127,6 +127,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, > uint32_t psr = pstate_read(env); > int i; > int el = arm_current_el(env); > + const char *ns_status; > > cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", > env->pc, env->xregs[31]); > @@ -138,12 +139,20 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, > cpu_fprintf(f, " "); > } > } > - cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c EL%d%c\n", > + > + if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { > + ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; > + } else { > + ns_status = ""; > + } Looks fine to me. I might of gone for a default: const char *ns_status = "legacy"; ... if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; } But otherwise: Reviewed-by: Alex Bennée > psr, > psr & PSTATE_N ? 'N' : '-', > psr & PSTATE_Z ? 'Z' : '-', > psr & PSTATE_C ? 'C' : '-', > psr & PSTATE_V ? 'V' : '-', > + ns_status, > el, > psr & PSTATE_SP ? 'h' : 't'); > > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 9f1d740..5f2346a 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -11556,6 +11556,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, > CPUARMState *env = &cpu->env; > int i; > uint32_t psr; > + const char *ns_status; > > if (is_a64(env)) { > aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags); > @@ -11570,13 +11571,22 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, > cpu_fprintf(f, " "); > } > psr = cpsr_read(env); > - cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n", > + > + if (arm_feature(env, ARM_FEATURE_EL3) && > + (psr & CPSR_M) != ARM_CPU_MODE_MON) { > + ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; > + } else { > + ns_status = ""; > + } > + > + cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", > psr, > psr & (1 << 31) ? 'N' : '-', > psr & (1 << 30) ? 'Z' : '-', > psr & (1 << 29) ? 'C' : '-', > psr & (1 << 28) ? 'V' : '-', > psr & CPSR_T ? 'T' : 'A', > + ns_status, > cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); > > if (flags & CPU_DUMP_FPU) { -- Alex Bennée