* [PATCH v2 0/3] Reformatted Sparc GDB XML patches.
@ 2025-07-11 15:51 unisono
2025-07-11 15:51 ` [PATCH v2 1/3] Adds the GDB register XML files for Sparc64 unisono
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: unisono @ 2025-07-11 15:51 UTC (permalink / raw)
To: qemu-devel
Cc: alex.bennee, atar4qemu, laurent, mark.cave-ayland, philmd, Rot127
From: Rot127 <unisono@quyllur.org>
Adds Sparc XML register files from GDB.
The xml files are copied from binutils-gdb.
The `*-core.xml` files are assembled from the sparc32-fpu.xml, sparc32-cp0.xml etc.
to match the registers defined by QEMU.
The addition is necessary if one wants to use the TCG plugins
with Sparc, because reading registers via the plugin API
just queries GDB.
The GDB stub initializes its register file with the `*-core.xml` files.
If they don't exist it returns no data.
Also relevant for debugging I assume.
v2:
Fixup for https://lore.kernel.org/qemu-devel/4887cd10-6126-489f-9e68-85b3ecdf0b3d@quyllur.org/
It removes the unused `*-fpu-.xml` and `*-cp0-.xml` and splits up the patches for each target.
Rot127 (3):
Adds the GDB register XML files for Sparc64.
Adds the GDB register XML files for Sparc32.
Assign the GDB register XML files of Sparc64 to Sparc32plus.
configs/targets/sparc-linux-user.mak | 1 +
configs/targets/sparc-softmmu.mak | 1 +
configs/targets/sparc32plus-linux-user.mak | 1 +
configs/targets/sparc64-linux-user.mak | 1 +
configs/targets/sparc64-softmmu.mak | 1 +
gdb-xml/sparc32-core.xml | 84 ++++++++++++++++++
gdb-xml/sparc64-core.xml | 99 ++++++++++++++++++++++
target/sparc/cpu.c | 2 +
8 files changed, 190 insertions(+)
create mode 100644 gdb-xml/sparc32-core.xml
create mode 100644 gdb-xml/sparc64-core.xml
--
2.50.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/3] Adds the GDB register XML files for Sparc64.
2025-07-11 15:51 [PATCH v2 0/3] Reformatted Sparc GDB XML patches unisono
@ 2025-07-11 15:51 ` unisono
2025-07-14 10:56 ` Alex Bennée
2025-07-11 15:51 ` [PATCH v2 2/3] Adds the GDB register XML files for Sparc32 unisono
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: unisono @ 2025-07-11 15:51 UTC (permalink / raw)
To: qemu-devel
Cc: alex.bennee, atar4qemu, laurent, mark.cave-ayland, philmd, Rot127
From: Rot127 <unisono@quyllur.org>
Commit 1/3
Signed-off-by: Rot127 <unisono@quyllur.org>
---
configs/targets/sparc64-linux-user.mak | 1 +
configs/targets/sparc64-softmmu.mak | 1 +
gdb-xml/sparc64-core.xml | 99 ++++++++++++++++++++++++++
target/sparc/cpu.c | 1 +
4 files changed, 102 insertions(+)
create mode 100644 gdb-xml/sparc64-core.xml
diff --git a/configs/targets/sparc64-linux-user.mak b/configs/targets/sparc64-linux-user.mak
index 64ea04e3e2..7c2ecb7be0 100644
--- a/configs/targets/sparc64-linux-user.mak
+++ b/configs/targets/sparc64-linux-user.mak
@@ -4,4 +4,5 @@ TARGET_ABI_DIR=sparc
TARGET_SYSTBL_ABI=common,64
TARGET_SYSTBL=syscall.tbl
TARGET_BIG_ENDIAN=y
+TARGET_XML_FILES=gdb-xml/sparc64-core.xml
TARGET_LONG_BITS=64
diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak
index 2504e31ae3..d9d51d21e5 100644
--- a/configs/targets/sparc64-softmmu.mak
+++ b/configs/targets/sparc64-softmmu.mak
@@ -1,4 +1,5 @@
TARGET_ARCH=sparc64
TARGET_BASE_ARCH=sparc
TARGET_BIG_ENDIAN=y
+TARGET_XML_FILES=gdb-xml/sparc64-core.xml
TARGET_LONG_BITS=64
diff --git a/gdb-xml/sparc64-core.xml b/gdb-xml/sparc64-core.xml
new file mode 100644
index 0000000000..375b9bb0cc
--- /dev/null
+++ b/gdb-xml/sparc64-core.xml
@@ -0,0 +1,99 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2013-2025 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.sparc.core">
+ <reg name="g0" bitsize="64" type="uint64" regnum="0"/>
+ <reg name="g1" bitsize="64" type="uint64" regnum="1"/>
+ <reg name="g2" bitsize="64" type="uint64" regnum="2"/>
+ <reg name="g3" bitsize="64" type="uint64" regnum="3"/>
+ <reg name="g4" bitsize="64" type="uint64" regnum="4"/>
+ <reg name="g5" bitsize="64" type="uint64" regnum="5"/>
+ <reg name="g6" bitsize="64" type="uint64" regnum="6"/>
+ <reg name="g7" bitsize="64" type="uint64" regnum="7"/>
+ <reg name="o0" bitsize="64" type="uint64" regnum="8"/>
+ <reg name="o1" bitsize="64" type="uint64" regnum="9"/>
+ <reg name="o2" bitsize="64" type="uint64" regnum="10"/>
+ <reg name="o3" bitsize="64" type="uint64" regnum="11"/>
+ <reg name="o4" bitsize="64" type="uint64" regnum="12"/>
+ <reg name="o5" bitsize="64" type="uint64" regnum="13"/>
+ <reg name="sp" bitsize="64" type="uint64" regnum="14"/>
+ <reg name="o7" bitsize="64" type="uint64" regnum="15"/>
+ <reg name="l0" bitsize="64" type="uint64" regnum="16"/>
+ <reg name="l1" bitsize="64" type="uint64" regnum="17"/>
+ <reg name="l2" bitsize="64" type="uint64" regnum="18"/>
+ <reg name="l3" bitsize="64" type="uint64" regnum="19"/>
+ <reg name="l4" bitsize="64" type="uint64" regnum="20"/>
+ <reg name="l5" bitsize="64" type="uint64" regnum="21"/>
+ <reg name="l6" bitsize="64" type="uint64" regnum="22"/>
+ <reg name="l7" bitsize="64" type="uint64" regnum="23"/>
+ <reg name="i0" bitsize="64" type="uint64" regnum="24"/>
+ <reg name="i1" bitsize="64" type="uint64" regnum="25"/>
+ <reg name="i2" bitsize="64" type="uint64" regnum="26"/>
+ <reg name="i3" bitsize="64" type="uint64" regnum="27"/>
+ <reg name="i4" bitsize="64" type="uint64" regnum="28"/>
+ <reg name="i5" bitsize="64" type="uint64" regnum="29"/>
+ <reg name="fp" bitsize="64" type="uint64" regnum="30"/>
+ <reg name="i7" bitsize="64" type="uint64" regnum="31"/>
+
+ <reg name="f0" bitsize="32" type="ieee_single" regnum="32"/>
+ <reg name="f1" bitsize="32" type="ieee_single" regnum="33"/>
+ <reg name="f2" bitsize="32" type="ieee_single" regnum="34"/>
+ <reg name="f3" bitsize="32" type="ieee_single" regnum="35"/>
+ <reg name="f4" bitsize="32" type="ieee_single" regnum="36"/>
+ <reg name="f5" bitsize="32" type="ieee_single" regnum="37"/>
+ <reg name="f6" bitsize="32" type="ieee_single" regnum="38"/>
+ <reg name="f7" bitsize="32" type="ieee_single" regnum="39"/>
+ <reg name="f8" bitsize="32" type="ieee_single" regnum="40"/>
+ <reg name="f9" bitsize="32" type="ieee_single" regnum="41"/>
+ <reg name="f10" bitsize="32" type="ieee_single" regnum="42"/>
+ <reg name="f11" bitsize="32" type="ieee_single" regnum="43"/>
+ <reg name="f12" bitsize="32" type="ieee_single" regnum="44"/>
+ <reg name="f13" bitsize="32" type="ieee_single" regnum="45"/>
+ <reg name="f14" bitsize="32" type="ieee_single" regnum="46"/>
+ <reg name="f15" bitsize="32" type="ieee_single" regnum="47"/>
+ <reg name="f16" bitsize="32" type="ieee_single" regnum="48"/>
+ <reg name="f17" bitsize="32" type="ieee_single" regnum="49"/>
+ <reg name="f18" bitsize="32" type="ieee_single" regnum="50"/>
+ <reg name="f19" bitsize="32" type="ieee_single" regnum="51"/>
+ <reg name="f20" bitsize="32" type="ieee_single" regnum="52"/>
+ <reg name="f21" bitsize="32" type="ieee_single" regnum="53"/>
+ <reg name="f22" bitsize="32" type="ieee_single" regnum="54"/>
+ <reg name="f23" bitsize="32" type="ieee_single" regnum="55"/>
+ <reg name="f24" bitsize="32" type="ieee_single" regnum="56"/>
+ <reg name="f25" bitsize="32" type="ieee_single" regnum="57"/>
+ <reg name="f26" bitsize="32" type="ieee_single" regnum="58"/>
+ <reg name="f27" bitsize="32" type="ieee_single" regnum="59"/>
+ <reg name="f28" bitsize="32" type="ieee_single" regnum="60"/>
+ <reg name="f29" bitsize="32" type="ieee_single" regnum="61"/>
+ <reg name="f30" bitsize="32" type="ieee_single" regnum="62"/>
+ <reg name="f31" bitsize="32" type="ieee_single" regnum="63"/>
+
+ <reg name="f32" bitsize="64" type="ieee_double" regnum="64"/>
+ <reg name="f34" bitsize="64" type="ieee_double" regnum="65"/>
+ <reg name="f36" bitsize="64" type="ieee_double" regnum="66"/>
+ <reg name="f38" bitsize="64" type="ieee_double" regnum="67"/>
+ <reg name="f40" bitsize="64" type="ieee_double" regnum="68"/>
+ <reg name="f42" bitsize="64" type="ieee_double" regnum="69"/>
+ <reg name="f44" bitsize="64" type="ieee_double" regnum="70"/>
+ <reg name="f46" bitsize="64" type="ieee_double" regnum="71"/>
+ <reg name="f48" bitsize="64" type="ieee_double" regnum="72"/>
+ <reg name="f50" bitsize="64" type="ieee_double" regnum="73"/>
+ <reg name="f52" bitsize="64" type="ieee_double" regnum="74"/>
+ <reg name="f54" bitsize="64" type="ieee_double" regnum="75"/>
+ <reg name="f56" bitsize="64" type="ieee_double" regnum="76"/>
+ <reg name="f58" bitsize="64" type="ieee_double" regnum="77"/>
+ <reg name="f60" bitsize="64" type="ieee_double" regnum="78"/>
+ <reg name="f62" bitsize="64" type="ieee_double" regnum="79"/>
+
+ <reg name="pc" bitsize="64" type="code_ptr" regnum="80"/>
+ <reg name="npc" bitsize="64" type="code_ptr" regnum="81"/>
+ <reg name="state" bitsize="64" type="uint64" regnum="82"/>
+ <reg name="fsr" bitsize="64" type="uint64" regnum="83"/>
+ <reg name="fprs" bitsize="64" type="uint64" regnum="84"/>
+ <reg name="y" bitsize="64" type="uint64" regnum="85"/>
+</feature>
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index ed7701b02f..245caf2de0 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -1090,6 +1090,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, const void *data)
cc->disas_set_info = cpu_sparc_disas_set_info;
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
+ cc->gdb_core_xml_file = "sparc64-core.xml";
cc->gdb_num_core_regs = 86;
#else
cc->gdb_num_core_regs = 72;
--
2.50.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] Adds the GDB register XML files for Sparc32.
2025-07-11 15:51 [PATCH v2 0/3] Reformatted Sparc GDB XML patches unisono
2025-07-11 15:51 ` [PATCH v2 1/3] Adds the GDB register XML files for Sparc64 unisono
@ 2025-07-11 15:51 ` unisono
2025-07-11 15:51 ` [PATCH v2 3/3] Assign the GDB register XML files of Sparc64 to Sparc32plus unisono
2025-07-14 10:59 ` [PATCH v2 0/3] Reformatted Sparc GDB XML patches Alex Bennée
3 siblings, 0 replies; 8+ messages in thread
From: unisono @ 2025-07-11 15:51 UTC (permalink / raw)
To: qemu-devel
Cc: alex.bennee, atar4qemu, laurent, mark.cave-ayland, philmd, Rot127
From: Rot127 <unisono@quyllur.org>
Commit 2/3
Signed-off-by: Rot127 <unisono@quyllur.org>
---
configs/targets/sparc-linux-user.mak | 1 +
configs/targets/sparc-softmmu.mak | 1 +
gdb-xml/sparc32-core.xml | 84 ++++++++++++++++++++++++++++
target/sparc/cpu.c | 1 +
4 files changed, 87 insertions(+)
create mode 100644 gdb-xml/sparc32-core.xml
diff --git a/configs/targets/sparc-linux-user.mak b/configs/targets/sparc-linux-user.mak
index 4ff4b7287d..4908ed7282 100644
--- a/configs/targets/sparc-linux-user.mak
+++ b/configs/targets/sparc-linux-user.mak
@@ -2,4 +2,5 @@ TARGET_ARCH=sparc
TARGET_SYSTBL_ABI=common,32
TARGET_SYSTBL=syscall.tbl
TARGET_BIG_ENDIAN=y
+TARGET_XML_FILES=gdb-xml/sparc32-core.xml
TARGET_LONG_BITS=32
diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak
index 57801faf1f..140d8462fa 100644
--- a/configs/targets/sparc-softmmu.mak
+++ b/configs/targets/sparc-softmmu.mak
@@ -1,3 +1,4 @@
TARGET_ARCH=sparc
TARGET_BIG_ENDIAN=y
+TARGET_XML_FILES=gdb-xml/sparc32-core.xml
TARGET_LONG_BITS=32
diff --git a/gdb-xml/sparc32-core.xml b/gdb-xml/sparc32-core.xml
new file mode 100644
index 0000000000..61964a79d1
--- /dev/null
+++ b/gdb-xml/sparc32-core.xml
@@ -0,0 +1,84 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2013-2025 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.sparc.core">
+ <reg name="g0" bitsize="32" type="uint32" regnum="0"/>
+ <reg name="g1" bitsize="32" type="uint32" regnum="1"/>
+ <reg name="g2" bitsize="32" type="uint32" regnum="2"/>
+ <reg name="g3" bitsize="32" type="uint32" regnum="3"/>
+ <reg name="g4" bitsize="32" type="uint32" regnum="4"/>
+ <reg name="g5" bitsize="32" type="uint32" regnum="5"/>
+ <reg name="g6" bitsize="32" type="uint32" regnum="6"/>
+ <reg name="g7" bitsize="32" type="uint32" regnum="7"/>
+ <reg name="o0" bitsize="32" type="uint32" regnum="8"/>
+ <reg name="o1" bitsize="32" type="uint32" regnum="9"/>
+ <reg name="o2" bitsize="32" type="uint32" regnum="10"/>
+ <reg name="o3" bitsize="32" type="uint32" regnum="11"/>
+ <reg name="o4" bitsize="32" type="uint32" regnum="12"/>
+ <reg name="o5" bitsize="32" type="uint32" regnum="13"/>
+ <reg name="sp" bitsize="32" type="uint32" regnum="14"/>
+ <reg name="o7" bitsize="32" type="uint32" regnum="15"/>
+ <reg name="l0" bitsize="32" type="uint32" regnum="16"/>
+ <reg name="l1" bitsize="32" type="uint32" regnum="17"/>
+ <reg name="l2" bitsize="32" type="uint32" regnum="18"/>
+ <reg name="l3" bitsize="32" type="uint32" regnum="19"/>
+ <reg name="l4" bitsize="32" type="uint32" regnum="20"/>
+ <reg name="l5" bitsize="32" type="uint32" regnum="21"/>
+ <reg name="l6" bitsize="32" type="uint32" regnum="22"/>
+ <reg name="l7" bitsize="32" type="uint32" regnum="23"/>
+ <reg name="i0" bitsize="32" type="uint32" regnum="24"/>
+ <reg name="i1" bitsize="32" type="uint32" regnum="25"/>
+ <reg name="i2" bitsize="32" type="uint32" regnum="26"/>
+ <reg name="i3" bitsize="32" type="uint32" regnum="27"/>
+ <reg name="i4" bitsize="32" type="uint32" regnum="28"/>
+ <reg name="i5" bitsize="32" type="uint32" regnum="29"/>
+ <reg name="fp" bitsize="32" type="uint32" regnum="30"/>
+ <reg name="i7" bitsize="32" type="uint32" regnum="31"/>
+
+ <reg name="f0" bitsize="32" type="ieee_single" regnum="32"/>
+ <reg name="f1" bitsize="32" type="ieee_single" regnum="33"/>
+ <reg name="f2" bitsize="32" type="ieee_single" regnum="34"/>
+ <reg name="f3" bitsize="32" type="ieee_single" regnum="35"/>
+ <reg name="f4" bitsize="32" type="ieee_single" regnum="36"/>
+ <reg name="f5" bitsize="32" type="ieee_single" regnum="37"/>
+ <reg name="f6" bitsize="32" type="ieee_single" regnum="38"/>
+ <reg name="f7" bitsize="32" type="ieee_single" regnum="39"/>
+ <reg name="f8" bitsize="32" type="ieee_single" regnum="40"/>
+ <reg name="f9" bitsize="32" type="ieee_single" regnum="41"/>
+ <reg name="f10" bitsize="32" type="ieee_single" regnum="42"/>
+ <reg name="f11" bitsize="32" type="ieee_single" regnum="43"/>
+ <reg name="f12" bitsize="32" type="ieee_single" regnum="44"/>
+ <reg name="f13" bitsize="32" type="ieee_single" regnum="45"/>
+ <reg name="f14" bitsize="32" type="ieee_single" regnum="46"/>
+ <reg name="f15" bitsize="32" type="ieee_single" regnum="47"/>
+ <reg name="f16" bitsize="32" type="ieee_single" regnum="48"/>
+ <reg name="f17" bitsize="32" type="ieee_single" regnum="49"/>
+ <reg name="f18" bitsize="32" type="ieee_single" regnum="50"/>
+ <reg name="f19" bitsize="32" type="ieee_single" regnum="51"/>
+ <reg name="f20" bitsize="32" type="ieee_single" regnum="52"/>
+ <reg name="f21" bitsize="32" type="ieee_single" regnum="53"/>
+ <reg name="f22" bitsize="32" type="ieee_single" regnum="54"/>
+ <reg name="f23" bitsize="32" type="ieee_single" regnum="55"/>
+ <reg name="f24" bitsize="32" type="ieee_single" regnum="56"/>
+ <reg name="f25" bitsize="32" type="ieee_single" regnum="57"/>
+ <reg name="f26" bitsize="32" type="ieee_single" regnum="58"/>
+ <reg name="f27" bitsize="32" type="ieee_single" regnum="59"/>
+ <reg name="f28" bitsize="32" type="ieee_single" regnum="60"/>
+ <reg name="f29" bitsize="32" type="ieee_single" regnum="61"/>
+ <reg name="f30" bitsize="32" type="ieee_single" regnum="62"/>
+ <reg name="f31" bitsize="32" type="ieee_single" regnum="63"/>
+
+ <reg name="y" bitsize="32" type="uint32" regnum="64"/>
+ <reg name="psr" bitsize="32" type="uint32" regnum="65"/>
+ <reg name="wim" bitsize="32" type="uint32" regnum="66"/>
+ <reg name="tbr" bitsize="32" type="uint32" regnum="67"/>
+ <reg name="pc" bitsize="32" type="code_ptr" regnum="68"/>
+ <reg name="npc" bitsize="32" type="code_ptr" regnum="69"/>
+ <reg name="fsr" bitsize="32" type="uint32" regnum="70"/>
+ <reg name="csr" bitsize="32" type="uint32" regnum="71"/>
+</feature>
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 245caf2de0..6d52be9263 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -1093,6 +1093,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, const void *data)
cc->gdb_core_xml_file = "sparc64-core.xml";
cc->gdb_num_core_regs = 86;
#else
+ cc->gdb_core_xml_file = "sparc32-core.xml";
cc->gdb_num_core_regs = 72;
#endif
cc->tcg_ops = &sparc_tcg_ops;
--
2.50.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] Assign the GDB register XML files of Sparc64 to Sparc32plus.
2025-07-11 15:51 [PATCH v2 0/3] Reformatted Sparc GDB XML patches unisono
2025-07-11 15:51 ` [PATCH v2 1/3] Adds the GDB register XML files for Sparc64 unisono
2025-07-11 15:51 ` [PATCH v2 2/3] Adds the GDB register XML files for Sparc32 unisono
@ 2025-07-11 15:51 ` unisono
2025-07-14 13:03 ` Richard Henderson
2025-07-14 10:59 ` [PATCH v2 0/3] Reformatted Sparc GDB XML patches Alex Bennée
3 siblings, 1 reply; 8+ messages in thread
From: unisono @ 2025-07-11 15:51 UTC (permalink / raw)
To: qemu-devel
Cc: alex.bennee, atar4qemu, laurent, mark.cave-ayland, philmd, Rot127
From: Rot127 <unisono@quyllur.org>
Commit 3/3
Signed-off-by: Rot127 <unisono@quyllur.org>
---
configs/targets/sparc32plus-linux-user.mak | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/targets/sparc32plus-linux-user.mak b/configs/targets/sparc32plus-linux-user.mak
index 7a16934fd1..0d9cf44652 100644
--- a/configs/targets/sparc32plus-linux-user.mak
+++ b/configs/targets/sparc32plus-linux-user.mak
@@ -5,4 +5,5 @@ TARGET_ABI_DIR=sparc
TARGET_SYSTBL_ABI=common,32
TARGET_SYSTBL=syscall.tbl
TARGET_BIG_ENDIAN=y
+TARGET_XML_FILES=gdb-xml/sparc64-core.xml
TARGET_LONG_BITS=64
--
2.50.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/3] Adds the GDB register XML files for Sparc64.
2025-07-11 15:51 ` [PATCH v2 1/3] Adds the GDB register XML files for Sparc64 unisono
@ 2025-07-14 10:56 ` Alex Bennée
0 siblings, 0 replies; 8+ messages in thread
From: Alex Bennée @ 2025-07-14 10:56 UTC (permalink / raw)
To: unisono; +Cc: qemu-devel, atar4qemu, laurent, mark.cave-ayland, philmd
unisono@quyllur.org writes:
> From: Rot127 <unisono@quyllur.org>
>
> Commit 1/3
>
> Signed-off-by: Rot127 <unisono@quyllur.org>
I've queued this one to my current PR and cleaned up the commit message
to:
gdbstub: add the GDB register XML files for sparc64.
Signed-off-by: Rot127 <unisono@quyllur.org>
Message-ID: <20250711155141.62916-2-unisono@quyllur.org>
[AJB: clean up commit msg]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
It's ok to have single line commit messages when the title can
encapsulate everything you need to know. Extra stuff like Commit 1/3 is
just noise in the commit log.
> ---
> configs/targets/sparc64-linux-user.mak | 1 +
> configs/targets/sparc64-softmmu.mak | 1 +
> gdb-xml/sparc64-core.xml | 99 ++++++++++++++++++++++++++
> target/sparc/cpu.c | 1 +
> 4 files changed, 102 insertions(+)
> create mode 100644 gdb-xml/sparc64-core.xml
>
> diff --git a/configs/targets/sparc64-linux-user.mak b/configs/targets/sparc64-linux-user.mak
> index 64ea04e3e2..7c2ecb7be0 100644
> --- a/configs/targets/sparc64-linux-user.mak
> +++ b/configs/targets/sparc64-linux-user.mak
> @@ -4,4 +4,5 @@ TARGET_ABI_DIR=sparc
> TARGET_SYSTBL_ABI=common,64
> TARGET_SYSTBL=syscall.tbl
> TARGET_BIG_ENDIAN=y
> +TARGET_XML_FILES=gdb-xml/sparc64-core.xml
> TARGET_LONG_BITS=64
> diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak
> index 2504e31ae3..d9d51d21e5 100644
> --- a/configs/targets/sparc64-softmmu.mak
> +++ b/configs/targets/sparc64-softmmu.mak
> @@ -1,4 +1,5 @@
> TARGET_ARCH=sparc64
> TARGET_BASE_ARCH=sparc
> TARGET_BIG_ENDIAN=y
> +TARGET_XML_FILES=gdb-xml/sparc64-core.xml
> TARGET_LONG_BITS=64
> diff --git a/gdb-xml/sparc64-core.xml b/gdb-xml/sparc64-core.xml
> new file mode 100644
> index 0000000000..375b9bb0cc
> --- /dev/null
> +++ b/gdb-xml/sparc64-core.xml
> @@ -0,0 +1,99 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2013-2025 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.sparc.core">
> + <reg name="g0" bitsize="64" type="uint64" regnum="0"/>
> + <reg name="g1" bitsize="64" type="uint64" regnum="1"/>
> + <reg name="g2" bitsize="64" type="uint64" regnum="2"/>
> + <reg name="g3" bitsize="64" type="uint64" regnum="3"/>
> + <reg name="g4" bitsize="64" type="uint64" regnum="4"/>
> + <reg name="g5" bitsize="64" type="uint64" regnum="5"/>
> + <reg name="g6" bitsize="64" type="uint64" regnum="6"/>
> + <reg name="g7" bitsize="64" type="uint64" regnum="7"/>
> + <reg name="o0" bitsize="64" type="uint64" regnum="8"/>
> + <reg name="o1" bitsize="64" type="uint64" regnum="9"/>
> + <reg name="o2" bitsize="64" type="uint64" regnum="10"/>
> + <reg name="o3" bitsize="64" type="uint64" regnum="11"/>
> + <reg name="o4" bitsize="64" type="uint64" regnum="12"/>
> + <reg name="o5" bitsize="64" type="uint64" regnum="13"/>
> + <reg name="sp" bitsize="64" type="uint64" regnum="14"/>
> + <reg name="o7" bitsize="64" type="uint64" regnum="15"/>
> + <reg name="l0" bitsize="64" type="uint64" regnum="16"/>
> + <reg name="l1" bitsize="64" type="uint64" regnum="17"/>
> + <reg name="l2" bitsize="64" type="uint64" regnum="18"/>
> + <reg name="l3" bitsize="64" type="uint64" regnum="19"/>
> + <reg name="l4" bitsize="64" type="uint64" regnum="20"/>
> + <reg name="l5" bitsize="64" type="uint64" regnum="21"/>
> + <reg name="l6" bitsize="64" type="uint64" regnum="22"/>
> + <reg name="l7" bitsize="64" type="uint64" regnum="23"/>
> + <reg name="i0" bitsize="64" type="uint64" regnum="24"/>
> + <reg name="i1" bitsize="64" type="uint64" regnum="25"/>
> + <reg name="i2" bitsize="64" type="uint64" regnum="26"/>
> + <reg name="i3" bitsize="64" type="uint64" regnum="27"/>
> + <reg name="i4" bitsize="64" type="uint64" regnum="28"/>
> + <reg name="i5" bitsize="64" type="uint64" regnum="29"/>
> + <reg name="fp" bitsize="64" type="uint64" regnum="30"/>
> + <reg name="i7" bitsize="64" type="uint64" regnum="31"/>
> +
> + <reg name="f0" bitsize="32" type="ieee_single" regnum="32"/>
> + <reg name="f1" bitsize="32" type="ieee_single" regnum="33"/>
> + <reg name="f2" bitsize="32" type="ieee_single" regnum="34"/>
> + <reg name="f3" bitsize="32" type="ieee_single" regnum="35"/>
> + <reg name="f4" bitsize="32" type="ieee_single" regnum="36"/>
> + <reg name="f5" bitsize="32" type="ieee_single" regnum="37"/>
> + <reg name="f6" bitsize="32" type="ieee_single" regnum="38"/>
> + <reg name="f7" bitsize="32" type="ieee_single" regnum="39"/>
> + <reg name="f8" bitsize="32" type="ieee_single" regnum="40"/>
> + <reg name="f9" bitsize="32" type="ieee_single" regnum="41"/>
> + <reg name="f10" bitsize="32" type="ieee_single" regnum="42"/>
> + <reg name="f11" bitsize="32" type="ieee_single" regnum="43"/>
> + <reg name="f12" bitsize="32" type="ieee_single" regnum="44"/>
> + <reg name="f13" bitsize="32" type="ieee_single" regnum="45"/>
> + <reg name="f14" bitsize="32" type="ieee_single" regnum="46"/>
> + <reg name="f15" bitsize="32" type="ieee_single" regnum="47"/>
> + <reg name="f16" bitsize="32" type="ieee_single" regnum="48"/>
> + <reg name="f17" bitsize="32" type="ieee_single" regnum="49"/>
> + <reg name="f18" bitsize="32" type="ieee_single" regnum="50"/>
> + <reg name="f19" bitsize="32" type="ieee_single" regnum="51"/>
> + <reg name="f20" bitsize="32" type="ieee_single" regnum="52"/>
> + <reg name="f21" bitsize="32" type="ieee_single" regnum="53"/>
> + <reg name="f22" bitsize="32" type="ieee_single" regnum="54"/>
> + <reg name="f23" bitsize="32" type="ieee_single" regnum="55"/>
> + <reg name="f24" bitsize="32" type="ieee_single" regnum="56"/>
> + <reg name="f25" bitsize="32" type="ieee_single" regnum="57"/>
> + <reg name="f26" bitsize="32" type="ieee_single" regnum="58"/>
> + <reg name="f27" bitsize="32" type="ieee_single" regnum="59"/>
> + <reg name="f28" bitsize="32" type="ieee_single" regnum="60"/>
> + <reg name="f29" bitsize="32" type="ieee_single" regnum="61"/>
> + <reg name="f30" bitsize="32" type="ieee_single" regnum="62"/>
> + <reg name="f31" bitsize="32" type="ieee_single" regnum="63"/>
> +
> + <reg name="f32" bitsize="64" type="ieee_double" regnum="64"/>
> + <reg name="f34" bitsize="64" type="ieee_double" regnum="65"/>
> + <reg name="f36" bitsize="64" type="ieee_double" regnum="66"/>
> + <reg name="f38" bitsize="64" type="ieee_double" regnum="67"/>
> + <reg name="f40" bitsize="64" type="ieee_double" regnum="68"/>
> + <reg name="f42" bitsize="64" type="ieee_double" regnum="69"/>
> + <reg name="f44" bitsize="64" type="ieee_double" regnum="70"/>
> + <reg name="f46" bitsize="64" type="ieee_double" regnum="71"/>
> + <reg name="f48" bitsize="64" type="ieee_double" regnum="72"/>
> + <reg name="f50" bitsize="64" type="ieee_double" regnum="73"/>
> + <reg name="f52" bitsize="64" type="ieee_double" regnum="74"/>
> + <reg name="f54" bitsize="64" type="ieee_double" regnum="75"/>
> + <reg name="f56" bitsize="64" type="ieee_double" regnum="76"/>
> + <reg name="f58" bitsize="64" type="ieee_double" regnum="77"/>
> + <reg name="f60" bitsize="64" type="ieee_double" regnum="78"/>
> + <reg name="f62" bitsize="64" type="ieee_double" regnum="79"/>
> +
> + <reg name="pc" bitsize="64" type="code_ptr" regnum="80"/>
> + <reg name="npc" bitsize="64" type="code_ptr" regnum="81"/>
> + <reg name="state" bitsize="64" type="uint64" regnum="82"/>
> + <reg name="fsr" bitsize="64" type="uint64" regnum="83"/>
> + <reg name="fprs" bitsize="64" type="uint64" regnum="84"/>
> + <reg name="y" bitsize="64" type="uint64" regnum="85"/>
> +</feature>
> diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
> index ed7701b02f..245caf2de0 100644
> --- a/target/sparc/cpu.c
> +++ b/target/sparc/cpu.c
> @@ -1090,6 +1090,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, const void *data)
> cc->disas_set_info = cpu_sparc_disas_set_info;
>
> #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
> + cc->gdb_core_xml_file = "sparc64-core.xml";
> cc->gdb_num_core_regs = 86;
> #else
> cc->gdb_num_core_regs = 72;
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/3] Reformatted Sparc GDB XML patches.
2025-07-11 15:51 [PATCH v2 0/3] Reformatted Sparc GDB XML patches unisono
` (2 preceding siblings ...)
2025-07-11 15:51 ` [PATCH v2 3/3] Assign the GDB register XML files of Sparc64 to Sparc32plus unisono
@ 2025-07-14 10:59 ` Alex Bennée
2025-07-14 16:42 ` Rot127
3 siblings, 1 reply; 8+ messages in thread
From: Alex Bennée @ 2025-07-14 10:59 UTC (permalink / raw)
To: unisono; +Cc: qemu-devel, atar4qemu, laurent, mark.cave-ayland, philmd
unisono@quyllur.org writes:
> From: Rot127 <unisono@quyllur.org>
>
> Adds Sparc XML register files from GDB.
<snip>
> Adds the GDB register XML files for Sparc32.
> Assign the GDB register XML files of Sparc64 to Sparc32plus.
I'm holding of these two until I can get sparc32-linux-user tested. Our
coverage isn't currently great due to not having cross compilers. For
sparc32plus specifically is the sparc64 xml going to work given it is
using a 32 bit ABI.
What testing have you done with these two?
>
> configs/targets/sparc-linux-user.mak | 1 +
> configs/targets/sparc-softmmu.mak | 1 +
> configs/targets/sparc32plus-linux-user.mak | 1 +
> configs/targets/sparc64-linux-user.mak | 1 +
> configs/targets/sparc64-softmmu.mak | 1 +
> gdb-xml/sparc32-core.xml | 84 ++++++++++++++++++
> gdb-xml/sparc64-core.xml | 99 ++++++++++++++++++++++
> target/sparc/cpu.c | 2 +
> 8 files changed, 190 insertions(+)
> create mode 100644 gdb-xml/sparc32-core.xml
> create mode 100644 gdb-xml/sparc64-core.xml
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 3/3] Assign the GDB register XML files of Sparc64 to Sparc32plus.
2025-07-11 15:51 ` [PATCH v2 3/3] Assign the GDB register XML files of Sparc64 to Sparc32plus unisono
@ 2025-07-14 13:03 ` Richard Henderson
0 siblings, 0 replies; 8+ messages in thread
From: Richard Henderson @ 2025-07-14 13:03 UTC (permalink / raw)
To: unisono, qemu-devel
Cc: alex.bennee, atar4qemu, laurent, mark.cave-ayland, philmd
On 7/11/25 09:51, unisono@quyllur.org wrote:
> From: Rot127 <unisono@quyllur.org>
>
> Commit 3/3
>
> Signed-off-by: Rot127 <unisono@quyllur.org>
> ---
> configs/targets/sparc32plus-linux-user.mak | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/configs/targets/sparc32plus-linux-user.mak b/configs/targets/sparc32plus-linux-user.mak
> index 7a16934fd1..0d9cf44652 100644
> --- a/configs/targets/sparc32plus-linux-user.mak
> +++ b/configs/targets/sparc32plus-linux-user.mak
> @@ -5,4 +5,5 @@ TARGET_ABI_DIR=sparc
> TARGET_SYSTBL_ABI=common,32
> TARGET_SYSTBL=syscall.tbl
> TARGET_BIG_ENDIAN=y
> +TARGET_XML_FILES=gdb-xml/sparc64-core.xml
> TARGET_LONG_BITS=64
This isn't used, because the ifdefs in sparc_cpu_class_init are wrong.
r~
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/3] Reformatted Sparc GDB XML patches.
2025-07-14 10:59 ` [PATCH v2 0/3] Reformatted Sparc GDB XML patches Alex Bennée
@ 2025-07-14 16:42 ` Rot127
0 siblings, 0 replies; 8+ messages in thread
From: Rot127 @ 2025-07-14 16:42 UTC (permalink / raw)
To: Alex Bennée; +Cc: qemu-devel, atar4qemu, laurent, mark.cave-ayland, philmd
> What testing have you done with these two?
None with Sparc32 and Sparc32plus. Also because I don't have immediate
access to a toolchain. But I have to do Sparc32 eventually as well and
can report back then.
For Sparc64 I use it in a the TCG plugin as described.
And it works as expected.
But haven't tested more unfortunately.
I wanted to get the patches out early, so you can consider adding it
into v10.1.
On 7/14/25 05:59, Alex Bennée wrote:
> unisono@quyllur.org writes:
>
>> From: Rot127 <unisono@quyllur.org>
>>
>> Adds Sparc XML register files from GDB.
> <snip>
>> Adds the GDB register XML files for Sparc32.
>> Assign the GDB register XML files of Sparc64 to Sparc32plus.
>
> I'm holding of these two until I can get sparc32-linux-user tested. Our
> coverage isn't currently great due to not having cross compilers. For
> sparc32plus specifically is the sparc64 xml going to work given it is
> using a 32 bit ABI.
>
> What testing have you done with these two?
>
>>
>> configs/targets/sparc-linux-user.mak | 1 +
>> configs/targets/sparc-softmmu.mak | 1 +
>> configs/targets/sparc32plus-linux-user.mak | 1 +
>> configs/targets/sparc64-linux-user.mak | 1 +
>> configs/targets/sparc64-softmmu.mak | 1 +
>> gdb-xml/sparc32-core.xml | 84 ++++++++++++++++++
>> gdb-xml/sparc64-core.xml | 99 ++++++++++++++++++++++
>> target/sparc/cpu.c | 2 +
>> 8 files changed, 190 insertions(+)
>> create mode 100644 gdb-xml/sparc32-core.xml
>> create mode 100644 gdb-xml/sparc64-core.xml
>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-07-14 17:50 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
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2025-07-11 15:51 [PATCH v2 0/3] Reformatted Sparc GDB XML patches unisono
2025-07-11 15:51 ` [PATCH v2 1/3] Adds the GDB register XML files for Sparc64 unisono
2025-07-14 10:56 ` Alex Bennée
2025-07-11 15:51 ` [PATCH v2 2/3] Adds the GDB register XML files for Sparc32 unisono
2025-07-11 15:51 ` [PATCH v2 3/3] Assign the GDB register XML files of Sparc64 to Sparc32plus unisono
2025-07-14 13:03 ` Richard Henderson
2025-07-14 10:59 ` [PATCH v2 0/3] Reformatted Sparc GDB XML patches Alex Bennée
2025-07-14 16:42 ` Rot127
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