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Wed, 08 Jan 2025 07:26:35 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0f029072sm2470902066b.170.2025.01.08.07.26.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jan 2025 07:26:35 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 7DBFD5F8AC; Wed, 8 Jan 2025 15:26:34 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, Pierrick Bouvier , Alistair Francis , Kito Cheng , Richard Henderson , Keith Packard , Daniel Henrique Barboza , Thomas Huth Subject: Re: [PATCH 0/5] semihosting: Reduce target specific code In-Reply-To: <20250103171037.11265-1-philmd@linaro.org> ("Philippe =?utf-8?Q?Mathieu-Daud=C3=A9=22's?= message of "Fri, 3 Jan 2025 18:10:32 +0100") References: <20250103171037.11265-1-philmd@linaro.org> User-Agent: mu4e 1.12.8; emacs 29.4 Date: Wed, 08 Jan 2025 15:26:34 +0000 Message-ID: <87h669ba39.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Philippe Mathieu-Daud=C3=A9 writes: > This series makes semihosting config.c and console.c > target agnostic, building them once, removing symbol > collision of the following functions in the single > binary: Queued to semihosting/next, thanks. > - qemu_semihosting_chardev_init > - qemu_semihosting_config_options > - qemu_semihosting_config_opts > - qemu_semihosting_enable > - semihosting_arg_fallback > - semihosting_enabled > - semihosting_get_argc > - semihosting_get_target > > This function is still problematic, being built for > each target: > > - qemu_semihosting_guestfd_init > > Note, it depends on CONFIG_ARM_COMPATIBLE_SEMIHOSTING > which is target specific, so doesn't scale in a > heterogeneous setup like the ZynqMP machine, having > ARM cores with CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy and > MicroBlaze ones with CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dn. Does MicroBlaze even do semihosting? > I suppose the semihosting API needs rework to consider > the CPUClass? I'll let that investigation for the > maintainer ;) Hmm most of it is already handled as EXCP_SEMIHOST exceptions are dealt with withing the target specific exception handlers. do_common_semihosting could be renamed though - do_armc_semihosting() maybe? If we have the full list of CPUs at qemu_semihosting_chardev_init() time we could then selectively do the bits of qemu_semihosting_guestfd_init() depending on what combination we have. For normal open/read/write stuff I think they could co-exist. Two independent cores could still write to stdout (0) though. Fixing that would need a per-cpu semihosting config. > > Regards, > > Phil. > > Philippe Mathieu-Daud=C3=A9 (5): > semihosting/syscalls: Include missing 'exec/cpu-defs.h' header > semihosting/uaccess: Include missing 'exec/cpu-all.h' header > semihosting/arm-compat: Include missing 'cpu.h' header > semihosting/console: Avoid including 'cpu.h' > semihosting/meson: Build config.o and console.o once > > include/semihosting/console.h | 2 -- > include/semihosting/syscalls.h | 1 + > semihosting/arm-compat-semi.c | 1 + > semihosting/console.c | 3 ++- > semihosting/uaccess.c | 1 + > semihosting/meson.build | 9 ++++++--- > 6 files changed, 11 insertions(+), 6 deletions(-) --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro