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Tue, 1 Feb 2022 20:33:32 +0000 (GMT) References: <20211218194250.247633-1-richard.henderson@linaro.org> <20211218194250.247633-9-richard.henderson@linaro.org> User-agent: mu4e 1.7.6; emacs 28.0.91 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Subject: Re: [PATCH 08/20] tcg/i386: Implement avx512 variable shifts Date: Tue, 01 Feb 2022 20:33:29 +0000 In-reply-to: <20211218194250.247633-9-richard.henderson@linaro.org> Message-ID: <87h79iwcmb.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::330 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > AVX512VL has VPSRAVQ, and > AVX512BW has VPSLLVW, VPSRAVW, VPSRLVW. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e > --- > tcg/i386/tcg-target.c.inc | 32 ++++++++++++++++++++++++-------- > 1 file changed, 24 insertions(+), 8 deletions(-) > > diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc > index 316e550b38..7b9302fcc2 100644 > --- a/tcg/i386/tcg-target.c.inc > +++ b/tcg/i386/tcg-target.c.inc > @@ -418,9 +418,13 @@ static bool tcg_target_const_match(int64_t val, TCGT= ype type, int ct) > #define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16) > #define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW) > #define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL) > +#define OPC_VPSLLVW (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) > #define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16) > #define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW) > +#define OPC_VPSRAVW (0x11 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) > #define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16) > +#define OPC_VPSRAVQ (0x46 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) > +#define OPC_VPSRLVW (0x10 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX) > #define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16) > #define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW) > #define OPC_VZEROUPPER (0x77 | P_EXT) > @@ -2742,16 +2746,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpco= de opc, > OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2 > }; > static int const shlv_insn[4] =3D { > - /* TODO: AVX512 adds support for MO_16. */ > - OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ > + OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ > }; > static int const shrv_insn[4] =3D { > - /* TODO: AVX512 adds support for MO_16. */ > - OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ > + OPC_UD2, OPC_VPSRLVW, OPC_VPSRLVD, OPC_VPSRLVQ > }; > static int const sarv_insn[4] =3D { > - /* TODO: AVX512 adds support for MO_16, MO_64. */ > - OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2 > + OPC_UD2, OPC_VPSRAVW, OPC_VPSRAVD, OPC_VPSRAVQ > }; > static int const shls_insn[4] =3D { > OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ > @@ -3242,9 +3243,24 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType typ= e, unsigned vece) >=20=20 > case INDEX_op_shlv_vec: > case INDEX_op_shrv_vec: > - return have_avx2 && vece >=3D MO_32; > + switch (vece) { > + case MO_16: > + return have_avx512bw; > + case MO_32: > + case MO_64: > + return have_avx2; > + } > + return 0; > case INDEX_op_sarv_vec: > - return have_avx2 && vece =3D=3D MO_32; > + switch (vece) { > + case MO_16: > + return have_avx512bw; > + case MO_32: > + return have_avx2; > + case MO_64: > + return have_avx512vl; > + } > + return 0; > case INDEX_op_rotlv_vec: > case INDEX_op_rotrv_vec: > return have_avx2 && vece >=3D MO_32 ? -1 : 0; --=20 Alex Benn=C3=A9e