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Mon, 13 Sep 2021 07:08:32 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id f5sm6906898wmb.47.2021.09.13.07.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 07:08:32 -0700 (PDT) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 5F01E1FF96; Mon, 13 Sep 2021 15:08:31 +0100 (BST) References: <20210903145938.1321571-1-alex.bennee@linaro.org> <36bc7691-c0d9-9e18-dade-4d95405dcd62@linaro.org> <871r5swztj.fsf@linaro.org> User-agent: mu4e 1.7.0; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Subject: Re: [PATCH] accel/tcg: assert insn_idx will always be valid before plugin_inject_cb Date: Mon, 13 Sep 2021 15:06:03 +0100 In-reply-to: Message-ID: <87h7eova8w.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > On 9/13/21 3:06 AM, Alex Benn=C3=A9e wrote: >>> Also, existing strageness in insn_idx being incremented for non-insns? >> It shouldn't be - it's just using the presence of the memory >> instrumentation as a proxy for the start of a instruction and dealing >> with the slightly different start of block boundary. >>=20 >>> Should it be named something else? I haven't looked at how it's >>> really used in the end. >> We need the insn idx to find the registered callbacks for a given >> instruction later. We could maybe embed a metadata TCGOp that could >> track this for us but that might make TCG a bit more confusing as it >> doesn't really need that information? > > We have a metadata op for marking instruction boundaries already: > INDEX_op_insn_start. Hmm so we have a separate list for speedy access: /* list to quickly access the injected ops */ QSIMPLEQ_HEAD(, TCGOp) plugin_ops; I wonder if we should drop that and just scan QTAILQ_HEAD(, TCGOp) ops so we can be properly aligned with the current instruction. Alternatively we could just emit INDEX_op_insn_start to the plugin list as well? > > > r~ --=20 Alex Benn=C3=A9e