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Tue, 23 Mar 2021 12:27:49 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id u2sm25098896wrp.12.2021.03.23.12.27.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 12:27:48 -0700 (PDT) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id B59541FF7E; Tue, 23 Mar 2021 19:27:47 +0000 (GMT) References: <20210322140206.9513-1-cfontana@suse.de> <20210322140206.9513-40-cfontana@suse.de> User-agent: mu4e 1.5.11; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Claudio Fontana Subject: Re: [RFC v10 39/49] target/arm: add tcg cpu accel class Date: Tue, 23 Mar 2021 19:26:16 +0000 In-reply-to: <20210322140206.9513-40-cfontana@suse.de> Message-ID: <87h7l1isb0.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , Richard Henderson , qemu-devel@nongnu.org, Roman Bolshakov , Paolo Bonzini , Philippe =?utf-8?Q?Mathieu-D?= =?utf-8?Q?aud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Claudio Fontana writes: > move init, realizefn and reset code into it. w.r.t my testing this is fingered by bisect for causing: Running test qtest-aarch64/migration-test ERROR qtest-aarch64/migration-test - Bail out! ERROR:../../target/arm/tcg= /tcg-cpu.c:233:tcg_arm_init_accel_cpu: assertion failed: (object_class_by_n= ame(ACCEL_CPU_NAME("tcg")) =3D=3D OBJECT_CLASS(accel_cpu)) Broken pipe make: *** [Makefile.mtest:272: run-test-32] Error 1 The bisect log: git bisect start # bad: [474677f44c0d581381db57ff6030a6553f16db95] XXX target/arm: experim= ent refactoring cpu "max" git bisect bad 474677f44c0d581381db57ff6030a6553f16db95 # good: [5ca634afcf83215a9a54ca6e66032325b5ffb5f6] Merge remote-tracking = branch 'remotes/philmd/tags/sdmmc-20210322' into staging git bisect good 5ca634afcf83215a9a54ca6e66032325b5ffb5f6 # good: [bf31455e28246f6b9b732dc56f89e61895f6f4f0] i386: split svm_helper= into sysemu and stub-only user git bisect good bf31455e28246f6b9b732dc56f89e61895f6f4f0 # good: [903f6e1bdc20939d023d6b577875370023bcac5f] target/arm: move arm_c= pu_list to common_cpu git bisect good 903f6e1bdc20939d023d6b577875370023bcac5f # good: [1999c2ce6cc82200a39f6e41041f304eba5d4e7e] tests: device-introspe= ct-test: cope with ARM TCG-only devices git bisect good 1999c2ce6cc82200a39f6e41041f304eba5d4e7e # bad: [fa37cc7fbabcf4de1cc963530c75b0ea7a73139a] target/arm: cpu-sve: ne= w module git bisect bad fa37cc7fbabcf4de1cc963530c75b0ea7a73139a # good: [d0c4b7a7d2aa12537a06527692f10066b7acbed9] target/arm: create kvm= cpu accel class git bisect good d0c4b7a7d2aa12537a06527692f10066b7acbed9 # bad: [3288c8a8cfc8dd9999e7b5908eaebb561f0169eb] target/arm: add tcg cpu= accel class git bisect bad 3288c8a8cfc8dd9999e7b5908eaebb561f0169eb # good: [683b948d40bc81f1eaed27bef8631ab3f8a937d6] target/arm: move kvm p= ost init initialization to kvm cpu accel git bisect good 683b948d40bc81f1eaed27bef8631ab3f8a937d6 # first bad commit: [3288c8a8cfc8dd9999e7b5908eaebb561f0169eb] target/arm= : add tcg cpu accel class 3288c8a8cfc8dd9999e7b5908eaebb561f0169eb is the first bad commit commit 3288c8a8cfc8dd9999e7b5908eaebb561f0169eb Author: Claudio Fontana Date: Mon Mar 22 15:01:56 2021 +0100 target/arm: add tcg cpu accel class move init, realizefn and reset code into it. Signed-off-by: Claudio Fontana Cc: Paolo Bonzini Message-Id: <20210322140206.9513-40-cfontana@suse.de> target/arm/cpu.c | 44 +++---------------------------- target/arm/tcg/sysemu/tcg-cpu.c | 27 +++++++++++++++++++ target/arm/tcg/tcg-cpu-models.c | 11 +++++--- target/arm/tcg/tcg-cpu.c | 57 +++++++++++++++++++++++++++++++++++= ++++-- target/arm/tcg/tcg-cpu.h | 4 ++- 5 files changed, 96 insertions(+), 47 deletions(-) bisect run success > > Signed-off-by: Claudio Fontana > Cc: Paolo Bonzini > --- > target/arm/tcg/tcg-cpu.h | 4 ++- > target/arm/cpu.c | 44 ++----------------------- > target/arm/tcg/sysemu/tcg-cpu.c | 27 ++++++++++++++++ > target/arm/tcg/tcg-cpu-models.c | 11 +++++-- > target/arm/tcg/tcg-cpu.c | 57 +++++++++++++++++++++++++++++++-- > 5 files changed, 96 insertions(+), 47 deletions(-) > > diff --git a/target/arm/tcg/tcg-cpu.h b/target/arm/tcg/tcg-cpu.h > index d93c6a6749..dd08587949 100644 > --- a/target/arm/tcg/tcg-cpu.h > +++ b/target/arm/tcg/tcg-cpu.h > @@ -22,15 +22,17 @@ >=20=20 > #include "cpu.h" > #include "hw/core/tcg-cpu-ops.h" > +#include "hw/core/accel-cpu.h" >=20=20 > void arm_cpu_synchronize_from_tb(CPUState *cs, > const TranslationBlock *tb); >=20=20 > -extern struct TCGCPUOps arm_tcg_ops; > +void tcg_arm_init_accel_cpu(AccelCPUClass *accel_cpu, CPUClass *cc); >=20=20 > #ifndef CONFIG_USER_ONLY > /* Do semihosting call and set the appropriate return value. */ > void tcg_handle_semihosting(CPUState *cs); > +bool tcg_cpu_realizefn(CPUState *cs, Error **errp); >=20=20 > #endif /* !CONFIG_USER_ONLY */ >=20=20 > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 5e0f6bd01d..9248e096df 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -410,12 +410,6 @@ static void arm_cpu_reset(DeviceState *dev) > &env->vfp.fp_status_f16); > set_float_detect_tininess(float_tininess_before_rounding, > &env->vfp.standard_fp_status_f16); > - > - if (tcg_enabled()) { > - hw_breakpoint_update_all(cpu); > - hw_watchpoint_update_all(cpu); > - arm_rebuild_hflags(env); > - } > } >=20=20 > void arm_cpu_update_virq(ARMCPU *cpu) > @@ -576,10 +570,6 @@ static void arm_cpu_initfn(Object *obj) > cpu->dtb_compatible =3D "qemu,unknown"; > cpu->psci_version =3D 1; /* By default assume PSCI v0.1 */ > cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_NONE; > - > - if (tcg_enabled()) { > - cpu->psci_version =3D 2; /* TCG implements PSCI 0.2 */ > - } > } >=20=20 > static Property arm_cpu_gt_cntfrq_property =3D > @@ -868,34 +858,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) > Error *local_err =3D NULL; > bool no_aa32 =3D false; >=20=20 > - /* > - * If we needed to query the host kernel for the CPU features > - * then it's possible that might have failed in the initfn, but > - * this is the first point where we can report it. > - */ > - if (cpu->host_cpu_probe_failed) { > - error_setg(errp, "The 'host' CPU type can only be used with KVM"= ); > - return; > - } > - > -#ifndef CONFIG_USER_ONLY > - /* The NVIC and M-profile CPU are two halves of a single piece of > - * hardware; trying to use one without the other is a command line > - * error and will result in segfaults if not caught here. > - */ > - if (arm_feature(env, ARM_FEATURE_M)) { > - if (!env->nvic) { > - error_setg(errp, "This board cannot be used with Cortex-M CP= Us"); > - return; > - } > - } else { > - if (env->nvic) { > - error_setg(errp, "This board can only be used with Cortex-M = CPUs"); > - return; > - } > - } > - > -#ifdef CONFIG_TCG > +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) > { > uint64_t scale; >=20=20 > @@ -921,8 +884,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) > cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, = scale, > arm_gt_hvtimer_cb, cpu= ); > } > -#endif /* CONFIG_TCG */ > -#endif /* !CONFIG_USER_ONLY */ > +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ >=20=20 > cpu_exec_realizefn(cs, &local_err); > if (local_err !=3D NULL) { > @@ -1458,7 +1420,7 @@ static void arm_cpu_class_init(ObjectClass *oc, voi= d *data) > cc->disas_set_info =3D arm_disas_set_info; >=20=20 > #ifdef CONFIG_TCG > - cc->tcg_ops =3D &arm_tcg_ops; > + cc->init_accel_cpu =3D tcg_arm_init_accel_cpu; > #endif /* CONFIG_TCG */ >=20=20 > arm32_cpu_class_init(oc, data); > diff --git a/target/arm/tcg/sysemu/tcg-cpu.c b/target/arm/tcg/sysemu/tcg-= cpu.c > index 327b2a5073..115ac523dc 100644 > --- a/target/arm/tcg/sysemu/tcg-cpu.c > +++ b/target/arm/tcg/sysemu/tcg-cpu.c > @@ -19,10 +19,13 @@ > */ >=20=20 > #include "qemu/osdep.h" > +#include "qapi/error.h" > +#include "qemu/timer.h" > #include "cpu.h" > #include "semihosting/common-semi.h" > #include "qemu/log.h" > #include "tcg/tcg-cpu.h" > +#include "internals.h" >=20=20 > /* > * Do semihosting call and set the appropriate return value. All the > @@ -50,3 +53,27 @@ void tcg_handle_semihosting(CPUState *cs) > env->regs[15] +=3D env->thumb ? 2 : 4; > } > } > + > +bool tcg_cpu_realizefn(CPUState *cs, Error **errp) > +{ > + ARMCPU *cpu =3D ARM_CPU(cs); > + CPUARMState *env =3D &cpu->env; > + > + /* > + * The NVIC and M-profile CPU are two halves of a single piece of > + * hardware; trying to use one without the other is a command line > + * error and will result in segfaults if not caught here. > + */ > + if (arm_feature(env, ARM_FEATURE_M)) { > + if (!env->nvic) { > + error_setg(errp, "This board cannot be used with Cortex-M CP= Us"); > + return false; > + } > + } else { > + if (env->nvic) { > + error_setg(errp, "This board can only be used with Cortex-M = CPUs"); > + return false; > + } > + } > + return true; > +} > diff --git a/target/arm/tcg/tcg-cpu-models.c b/target/arm/tcg/tcg-cpu-mod= els.c > index 16ab5d5364..2f44fd1b41 100644 > --- a/target/arm/tcg/tcg-cpu-models.c > +++ b/target/arm/tcg/tcg-cpu-models.c > @@ -844,15 +844,20 @@ static struct TCGCPUOps arm_v7m_tcg_ops =3D { > #endif /* !CONFIG_USER_ONLY */ > }; >=20=20 > +static void arm_v7m_init_accel_cpu(AccelCPUClass *accel_cpu, CPUClass *c= c) > +{ > + g_assert(object_class_by_name(ACCEL_CPU_NAME("tcg")) =3D=3D OBJECT_C= LASS(accel_cpu)); > + > + cc->tcg_ops =3D &arm_v7m_tcg_ops; > +} > + > static void arm_v7m_class_init(ObjectClass *oc, void *data) > { > ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); > CPUClass *cc =3D CPU_CLASS(oc); >=20=20 > acc->info =3D data; > -#ifdef CONFIG_TCG > - cc->tcg_ops =3D &arm_v7m_tcg_ops; > -#endif /* CONFIG_TCG */ > + cc->init_accel_cpu =3D arm_v7m_init_accel_cpu; >=20=20 > cc->gdb_core_xml_file =3D "arm-m-profile.xml"; > } > diff --git a/target/arm/tcg/tcg-cpu.c b/target/arm/tcg/tcg-cpu.c > index 9fd996d908..d6c3a0ba41 100644 > --- a/target/arm/tcg/tcg-cpu.c > +++ b/target/arm/tcg/tcg-cpu.c > @@ -20,8 +20,8 @@ >=20=20 > #include "qemu/osdep.h" > #include "cpu.h" > +#include "qapi/error.h" > #include "tcg-cpu.h" > -#include "hw/core/tcg-cpu-ops.h" > #include "cpregs.h" > #include "internals.h" > #include "exec/exec-all.h" > @@ -212,7 +212,7 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) > return true; > } >=20=20 > -struct TCGCPUOps arm_tcg_ops =3D { > +static struct TCGCPUOps arm_tcg_ops =3D { > .initialize =3D arm_translate_init, > .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, > .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, > @@ -227,3 +227,56 @@ struct TCGCPUOps arm_tcg_ops =3D { > .debug_check_watchpoint =3D arm_debug_check_watchpoint, > #endif /* !CONFIG_USER_ONLY */ > }; > + > +void tcg_arm_init_accel_cpu(AccelCPUClass *accel_cpu, CPUClass *cc) > +{ > + g_assert(object_class_by_name(ACCEL_CPU_NAME("tcg")) =3D=3D OBJECT_C= LASS(accel_cpu)); > + > + cc->tcg_ops =3D &arm_tcg_ops; > +} > + > +static void tcg_cpu_instance_init(CPUState *cs) > +{ > + ARMCPU *cpu =3D ARM_CPU(cs); > + > + /* > + * this would be the place to move TCG-specific props > + * in future refactoring of cpu properties. > + */ > + > + cpu->psci_version =3D 2; /* TCG implements PSCI 0.2 */ > +} > + > +static void tcg_cpu_reset(CPUState *cs) > +{ > + ARMCPU *cpu =3D ARM_CPU(cs); > + CPUARMState *env =3D &cpu->env; > + > + hw_breakpoint_update_all(cpu); > + hw_watchpoint_update_all(cpu); > + arm_rebuild_hflags(env); > +} > + > +static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) > +{ > + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); > + > +#ifndef CONFIG_USER_ONLY > + acc->cpu_realizefn =3D tcg_cpu_realizefn; > +#endif /* CONFIG_USER_ONLY */ > + > + acc->cpu_instance_init =3D tcg_cpu_instance_init; > + acc->cpu_reset =3D tcg_cpu_reset; > +} > +static const TypeInfo tcg_cpu_accel_type_info =3D { > + .name =3D ACCEL_CPU_NAME("tcg"), > + > + .parent =3D TYPE_ACCEL_CPU, > + .class_init =3D tcg_cpu_accel_class_init, > + .abstract =3D true, > +}; > +static void tcg_cpu_accel_register_types(void) > +{ > + type_register_static(&tcg_cpu_accel_type_info); > +} > +type_init(tcg_cpu_accel_register_types); --=20 Alex Benn=C3=A9e