From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38106) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bGTnM-00081l-7U for qemu-devel@nongnu.org; Fri, 24 Jun 2016 12:17:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bGTn8-000484-9D for qemu-devel@nongnu.org; Fri, 24 Jun 2016 12:17:27 -0400 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]:37753) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bGTn8-00047t-2e for qemu-devel@nongnu.org; Fri, 24 Jun 2016 12:17:14 -0400 Received: by mail-wm0-x230.google.com with SMTP id a66so31976398wme.0 for ; Fri, 24 Jun 2016 09:17:14 -0700 (PDT) From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <20160618040343.19517-14-bobby.prani@gmail.com> Date: Fri, 24 Jun 2016 17:17:18 +0100 Message-ID: <87h9cizhm9.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [RFC v3 PATCH 13/14] aarch64: Generate fences for aarch64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Pranith Kumar Cc: Peter Maydell , "open list:ARM" , "open list:All patches CC here" , serge.fdrv@gmail.com, rth@twiddle.net Pranith Kumar writes: > Signed-off-by: Pranith Kumar > --- > target-arm/translate-a64.c | 18 +++++++++++++----- > 1 file changed, 13 insertions(+), 5 deletions(-) > > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c > index ce8141a..fa24bf2 100644 > --- a/target-arm/translate-a64.c > +++ b/target-arm/translate-a64.c > @@ -1250,7 +1250,7 @@ static void handle_sync(DisasContext *s, uint32_t insn, > return; > case 4: /* DSB */ > case 5: /* DMB */ > - /* We don't emulate caches so barriers are no-ops */ > + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); > return; > case 6: /* ISB */ > /* We need to break the TB after this insn to execute > @@ -1855,23 +1855,31 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) > } > tcg_addr = read_cpu_reg_sp(s, rn, 1); > > - /* Note that since TCG is single threaded load-acquire/store-release > - * semantics require no extra if (is_lasr) { ... } handling. > - */ > - > if (is_excl) { > if (!is_store) { > s->is_ldex = true; > gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair); > + if (is_lasr) { > + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_ACQ); > + } > } else { > + if (is_lasr) { > + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_REL); > + } > gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair); > } > } else { > TCGv_i64 tcg_rt = cpu_reg(s, rt); > if (is_store) { > + if (is_lasr) { > + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_REL); > + } > do_gpr_st(s, tcg_rt, tcg_addr, size); > } else { > do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false); > + if (is_lasr) { > + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_ACQ); > + } See the private email I sent you with the litmus tests. I think you'll need to confirm this is working as expected. > } > } > } -- Alex Bennée