From: "Alex Bennée" <alex.bennee@linaro.org>
To: Alvise Rigo <a.rigo@virtualopensystems.com>
Cc: mttcg@listserver.greensocs.com, claudio.fontana@huawei.com,
qemu-devel@nongnu.org, pbonzini@redhat.com,
jani.kokkonen@huawei.com, tech@virtualopensystems.com,
rth@twiddle.net
Subject: Re: [Qemu-devel] [RFC v6 03/14] Add CPUClass hook to set exclusive range
Date: Tue, 05 Jan 2016 16:42:23 +0000 [thread overview]
Message-ID: <87h9isc70w.fsf@linaro.org> (raw)
In-Reply-To: <1450082498-27109-4-git-send-email-a.rigo@virtualopensystems.com>
Alvise Rigo <a.rigo@virtualopensystems.com> writes:
> Allow each architecture to set the exclusive range at any LoadLink
> operation through a CPUClass hook.
nit: space or continue paragraph.
> This comes in handy to emulate, for instance, the exclusive monitor
> implemented in some ARM architectures (more precisely, the Exclusive
> Reservation Granule).
>
> Suggested-by: Jani Kokkonen <jani.kokkonen@huawei.com>
> Suggested-by: Claudio Fontana <claudio.fontana@huawei.com>
> Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/qom/cpu.h | 4 ++++
> qom/cpu.c | 7 +++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/include/qom/cpu.h b/include/qom/cpu.h
> index c6bb6b6..9e409ce 100644
> --- a/include/qom/cpu.h
> +++ b/include/qom/cpu.h
> @@ -175,6 +175,10 @@ typedef struct CPUClass {
> void (*cpu_exec_exit)(CPUState *cpu);
> bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
>
> + /* Atomic instruction handling */
> + void (*cpu_set_excl_protected_range)(CPUState *cpu, hwaddr addr,
> + hwaddr size);
> +
> void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
> } CPUClass;
>
> diff --git a/qom/cpu.c b/qom/cpu.c
> index fb80d13..a5c25a8 100644
> --- a/qom/cpu.c
> +++ b/qom/cpu.c
> @@ -203,6 +203,12 @@ static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req)
> return false;
> }
>
> +static void cpu_common_set_excl_range(CPUState *cpu, hwaddr addr, hwaddr size)
> +{
> + cpu->excl_protected_range.begin = addr;
> + cpu->excl_protected_range.end = addr + size;
> +}
> +
> void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
> int flags)
> {
> @@ -355,6 +361,7 @@ static void cpu_class_init(ObjectClass *klass, void *data)
> k->cpu_exec_enter = cpu_common_noop;
> k->cpu_exec_exit = cpu_common_noop;
> k->cpu_exec_interrupt = cpu_common_exec_interrupt;
> + k->cpu_set_excl_protected_range = cpu_common_set_excl_range;
> dc->realize = cpu_common_realizefn;
> /*
> * Reason: CPUs still need special care by board code: wiring up
--
Alex Bennée
next prev parent reply other threads:[~2016-01-05 16:42 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-14 8:41 [Qemu-devel] [RFC v6 00/14] Slow-path for atomic instruction translation Alvise Rigo
2015-12-14 8:41 ` [Qemu-devel] [RFC v6 01/14] exec.c: Add new exclusive bitmap to ram_list Alvise Rigo
2015-12-18 13:18 ` Alex Bennée
2015-12-18 13:47 ` alvise rigo
2015-12-14 8:41 ` [Qemu-devel] [RFC v6 02/14] softmmu: Add new TLB_EXCL flag Alvise Rigo
2016-01-05 16:10 ` Alex Bennée
2016-01-05 17:27 ` alvise rigo
2016-01-05 18:39 ` Alex Bennée
2015-12-14 8:41 ` [Qemu-devel] [RFC v6 03/14] Add CPUClass hook to set exclusive range Alvise Rigo
2016-01-05 16:42 ` Alex Bennée [this message]
2015-12-14 8:41 ` [Qemu-devel] [RFC v6 04/14] softmmu: Add helpers for a new slowpath Alvise Rigo
2016-01-06 15:16 ` Alex Bennée
2015-12-14 8:41 ` [Qemu-devel] [RFC v6 05/14] tcg: Create new runtime helpers for excl accesses Alvise Rigo
2015-12-14 9:40 ` Paolo Bonzini
2015-12-14 8:41 ` [Qemu-devel] [RFC v6 06/14] configure: Use slow-path for atomic only when the softmmu is enabled Alvise Rigo
2015-12-14 9:38 ` Paolo Bonzini
2015-12-14 9:39 ` Paolo Bonzini
2015-12-14 10:14 ` Laurent Vivier
2015-12-15 14:23 ` alvise rigo
2015-12-15 14:31 ` Paolo Bonzini
2015-12-15 15:18 ` Laurent Vivier
2015-12-14 8:41 ` [Qemu-devel] [RFC v6 07/14] target-arm: translate: Use ld/st excl for atomic insns Alvise Rigo
2016-01-06 17:11 ` Alex Bennée
2015-12-14 8:41 ` [Qemu-devel] [RFC v6 08/14] target-arm: Add atomic_clear helper for CLREX insn Alvise Rigo
2016-01-06 17:13 ` Alex Bennée
2016-01-06 17:27 ` alvise rigo
2015-12-14 8:41 ` [Qemu-devel] [RFC v6 09/14] softmmu: Add history of excl accesses Alvise Rigo
2015-12-14 9:35 ` Paolo Bonzini
2015-12-15 14:26 ` alvise rigo
2015-12-14 8:41 ` [Qemu-devel] [RFC v6 10/14] softmmu: Simplify helper_*_st_name, wrap unaligned code Alvise Rigo
2016-01-07 14:46 ` Alex Bennée
2016-01-07 15:09 ` alvise rigo
2016-01-07 16:35 ` Alex Bennée
2016-01-07 16:54 ` alvise rigo
2016-01-07 17:36 ` Alex Bennée
2016-01-08 11:19 ` Alex Bennée
2015-12-14 8:41 ` [Qemu-devel] [RFC v6 11/14] softmmu: Simplify helper_*_st_name, wrap MMIO code Alvise Rigo
2016-01-11 9:54 ` Alex Bennée
2016-01-11 10:19 ` alvise rigo
2015-12-14 8:41 ` [Qemu-devel] [RFC v6 12/14] softmmu: Simplify helper_*_st_name, wrap RAM code Alvise Rigo
2015-12-17 16:52 ` Alex Bennée
2015-12-17 17:13 ` alvise rigo
2015-12-17 20:20 ` Alex Bennée
2015-12-14 8:41 ` [Qemu-devel] [RFC v6 13/14] softmmu: Include MMIO/invalid exclusive accesses Alvise Rigo
2015-12-14 8:41 ` [Qemu-devel] [RFC v6 14/14] softmmu: Protect MMIO exclusive range Alvise Rigo
2015-12-14 9:33 ` [Qemu-devel] [RFC v6 00/14] Slow-path for atomic instruction translation Paolo Bonzini
2015-12-14 10:04 ` alvise rigo
2015-12-14 10:17 ` Paolo Bonzini
2015-12-15 13:59 ` alvise rigo
2015-12-15 14:18 ` Paolo Bonzini
2015-12-15 14:22 ` alvise rigo
2015-12-14 22:09 ` Andreas Tobler
2015-12-15 8:16 ` alvise rigo
2015-12-17 16:06 ` Alex Bennée
2015-12-17 16:16 ` alvise rigo
2016-01-06 18:00 ` Andrew Baumann
2016-01-07 10:21 ` alvise rigo
2016-01-07 10:22 ` Peter Maydell
2016-01-07 10:49 ` alvise rigo
2016-01-07 11:16 ` Peter Maydell
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