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From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
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Date: Wed, 28 Jan 2015 15:54:10 +0000
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Subject: Re: [Qemu-devel] [PATCH] FMULX should flushes operators to zero
	when FZ is set.
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To: Xiangyu Hu <libhu.so@gmail.com>
Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org


Xiangyu Hu <libhu.so@gmail.com> writes:

> The difference between FMULX and FMUL is that FMULX will return 2.0f when one operator is 
> FPInfinity and the other one is FPZero, whilst FMUL will return a Default NaN. Without 
> this patch, the emulation would result in inconsistency.
>
> Signed-off-by: Xiangyu Hu <libhu.so@gmail.com>
> ---
>  target-arm/helper-a64.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
> index 81066ca..ebd9247 100644
> --- a/target-arm/helper-a64.c
> +++ b/target-arm/helper-a64.c
> @@ -135,6 +135,9 @@ float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
>  {
>      float_status *fpst = fpstp;
>  
> +    a = float32_squash_input_denormal(a, fpst);
> +    b = float32_squash_input_denormal(b, fpst);
> +
>      if ((float32_is_zero(a) && float32_is_infinity(b)) ||
>          (float32_is_infinity(a) && float32_is_zero(b))) {
>          /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
> @@ -148,6 +151,9 @@ float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
>  {
>      float_status *fpst = fpstp;
>  
> +    a = float64_squash_input_denormal(a, fpst);
> +    b = float64_squash_input_denormal(b, fpst);
> +
>      if ((float64_is_zero(a) && float64_is_infinity(b)) ||
>          (float64_is_infinity(a) && float64_is_zero(b))) {
>          /* 2.0 with the sign bit set to sign(A) XOR sign(B) */

Do we have test cases that trip up here? It would be nice to include
them in our testing as the random nature of RISU has obviously failed to
trip up on this instruction.

-- 
Alex Bennée