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Tue, 09 Dec 2025 04:14:17 -0800 (PST) Received: from draig.lan ([185.126.160.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47a7da22878sm15178115e9.16.2025.12.09.04.14.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Dec 2025 04:14:17 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 684A85F747; Tue, 09 Dec 2025 12:14:16 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Mark Burton Cc: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Matheus Bernardino , Sid Manning , Brian Cain , QEMU Developers , Gustavo Bueno Romero , Richard Henderson Subject: Re: Record AS in full tlb In-Reply-To: (Mark Burton's message of "Tue, 9 Dec 2025 10:47:40 +0000") References: User-Agent: mu4e 1.12.14-pre3; emacs 30.1 Date: Tue, 09 Dec 2025 12:14:16 +0000 Message-ID: <87ikefhmxz.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Mark Burton writes: > Just posting this here for the discussion this afternoon. > > Cheers > Mark. > > > [2. 0001-Record-AddressSpace-in-full-tlb-so-access-to-MMIO-vi.patch --- t= ext/x-diff; 0001-Record-AddressSpace-in-full-tlb-so-access-to-MMIO-vi.patch= ]... We were discussing last week how we should break the dependency on CPUState for AddressSpaces while Gustavo was looking at adding the FEAT_MEC code. They are really a function of the machine where most CPUs will share the same set of views. However we still need a way to resolve the AS from the CPUs perspective. Copying inline for easier commenting: diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b09229dae8..4b1aa9df71 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1073,7 +1073,8 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, prot =3D full->prot; asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); section =3D address_space_translate_for_iotlb(cpu, asidx, paddr_page, - &xlat, &sz, full->attrs, &= prot); + &xlat, &sz, &full->attrs, + &full->as, &prot); assert(sz >=3D TARGET_PAGE_SIZE); =20 tlb_debug("vaddr=3D%016" VADDR_PRIx " paddr=3D0x" HWADDR_FMT_plx @@ -1294,13 +1295,13 @@ static inline void cpu_unaligned_access(CPUState *c= pu, vaddr addr, } =20 static MemoryRegionSection * -io_prepare(hwaddr *out_offset, CPUState *cpu, hwaddr xlat, +io_prepare(hwaddr *out_offset, CPUState *cpu, AddressSpace *as, hwaddr xla= t, MemTxAttrs attrs, vaddr addr, uintptr_t retaddr) { MemoryRegionSection *section; hwaddr mr_offset; =20 - section =3D iotlb_to_section(cpu, xlat, attrs); + section =3D iotlb_to_section(as, xlat, attrs); mr_offset =3D (xlat & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc =3D retaddr; if (!cpu->neg.can_do_io) { @@ -1618,7 +1619,7 @@ bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int= mmu_idx, /* We must have an iotlb entry for MMIO */ if (tlb_addr & TLB_MMIO) { MemoryRegionSection *section =3D - iotlb_to_section(cpu, full->xlat_section & ~TARGET_PAGE_MASK, + iotlb_to_section(full->as, full->xlat_section & ~TARGET_PAGE_M= ASK, full->attrs); data->is_io =3D true; data->mr =3D section->mr; @@ -2028,7 +2029,8 @@ static uint64_t do_ld_mmio_beN(CPUState *cpu, CPUTLBE= ntryFull *full, tcg_debug_assert(size > 0 && size <=3D 8); =20 attrs =3D full->attrs; - section =3D io_prepare(&mr_offset, cpu, full->xlat_section, attrs, add= r, ra); + section =3D io_prepare(&mr_offset, cpu, full->as, + full->xlat_section, attrs, addr, ra); mr =3D section->mr; =20 BQL_LOCK_GUARD(); @@ -2049,7 +2051,8 @@ static Int128 do_ld16_mmio_beN(CPUState *cpu, CPUTLBE= ntryFull *full, tcg_debug_assert(size > 8 && size <=3D 16); =20 attrs =3D full->attrs; - section =3D io_prepare(&mr_offset, cpu, full->xlat_section, attrs, add= r, ra); + section =3D io_prepare(&mr_offset, cpu, full->as, + full->xlat_section, attrs, addr, ra); mr =3D section->mr; =20 BQL_LOCK_GUARD(); @@ -2593,7 +2596,8 @@ static uint64_t do_st_mmio_leN(CPUState *cpu, CPUTLBE= ntryFull *full, tcg_debug_assert(size > 0 && size <=3D 8); =20 attrs =3D full->attrs; - section =3D io_prepare(&mr_offset, cpu, full->xlat_section, attrs, add= r, ra); + section =3D io_prepare(&mr_offset, cpu, full->as, + full->xlat_section, attrs, addr, ra); mr =3D section->mr; =20 BQL_LOCK_GUARD(); @@ -2613,7 +2617,8 @@ static uint64_t do_st16_mmio_leN(CPUState *cpu, CPUTL= BEntryFull *full, tcg_debug_assert(size > 8 && size <=3D 16); =20 attrs =3D full->attrs; - section =3D io_prepare(&mr_offset, cpu, full->xlat_section, attrs, add= r, ra); + section =3D io_prepare(&mr_offset, cpu, full->as, + full->xlat_section, attrs, addr, ra); mr =3D section->mr; =20 BQL_LOCK_GUARD(); diff --git a/include/accel/tcg/iommu.h b/include/accel/tcg/iommu.h index 90cfd6c0ed..ac50e50601 100644 --- a/include/accel/tcg/iommu.h +++ b/include/accel/tcg/iommu.h @@ -16,22 +16,23 @@ =20 /** * iotlb_to_section: - * @cpu: CPU performing the access + * @as: Address space to access * @index: TCG CPU IOTLB entry * * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that * it refers to. @index will have been initially created and returned * by memory_region_section_get_iotlb(). */ -MemoryRegionSection *iotlb_to_section(CPUState *cpu, - hwaddr index, MemTxAttrs attrs); +struct MemoryRegionSection *iotlb_to_section(AddressSpace *as, + hwaddr index, MemTxAttrs attr= s); =20 MemoryRegionSection *address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, hwaddr *xlat, hwaddr *plen, - MemTxAttrs attrs, + MemTxAttrs *attrs, + AddressSpace **as, int *prot); =20 hwaddr memory_region_section_get_iotlb(CPUState *cpu, diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c0ca4b6905..a27d8feefc 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -269,6 +269,8 @@ struct CPUTLBEntryFull { bool guarded; } arm; } extra; + + AddressSpace *as; }; =20 /* diff --git a/system/physmem.c b/system/physmem.c index cf7146b224..52156325d9 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -688,7 +688,8 @@ void tcg_iommu_init_notifier_list(CPUState *cpu) MemoryRegionSection * address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_ad= dr, hwaddr *xlat, hwaddr *plen, - MemTxAttrs attrs, int *prot) + MemTxAttrs *attrs, AddressSpace **as, + int *prot) { MemoryRegionSection *section; IOMMUMemoryRegion *iommu_mr; @@ -696,7 +697,8 @@ address_space_translate_for_iotlb(CPUState *cpu, int as= idx, hwaddr orig_addr, IOMMUTLBEntry iotlb; int iommu_idx; hwaddr addr =3D orig_addr; - AddressSpaceDispatch *d =3D address_space_to_dispatch(cpu->cpu_ases[as= idx].as); + *as =3D cpu->cpu_ases[asidx].as; + AddressSpaceDispatch *d =3D address_space_to_dispatch(*as); =20 for (;;) { section =3D address_space_translate_internal(d, addr, &addr, plen,= false); @@ -708,13 +710,13 @@ address_space_translate_for_iotlb(CPUState *cpu, int = asidx, hwaddr orig_addr, =20 imrc =3D memory_region_get_iommu_class_nocheck(iommu_mr); =20 - iommu_idx =3D imrc->attrs_to_index(iommu_mr, attrs); + iommu_idx =3D imrc->attrs_to_index(iommu_mr, *attrs); tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx); /* We need all the permissions, so pass IOMMU_NONE so the IOMMU * doesn't short-cut its translation table walk. */ if (imrc->translate_attr) { - iotlb =3D imrc->translate_attr(iommu_mr, addr, IOMMU_NONE, &at= trs); + iotlb =3D imrc->translate_attr(iommu_mr, addr, IOMMU_NONE, att= rs); } else { iotlb =3D imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_id= x); } @@ -735,7 +737,8 @@ address_space_translate_for_iotlb(CPUState *cpu, int as= idx, hwaddr orig_addr, goto translate_fail; } =20 - d =3D flatview_to_dispatch(address_space_to_flatview(iotlb.target_= as)); + *as =3D iotlb.target_as; + d =3D flatview_to_dispatch(address_space_to_flatview(*as)); } =20 assert(!memory_region_is_iommu(section->mr)); @@ -756,12 +759,12 @@ translate_fail: return &d->map.sections[PHYS_SECTION_UNASSIGNED]; } =20 -MemoryRegionSection *iotlb_to_section(CPUState *cpu, + +MemoryRegionSection *iotlb_to_section(AddressSpace *as, hwaddr index, MemTxAttrs attrs) { - int asidx =3D cpu_asidx_from_attrs(cpu, attrs); - CPUAddressSpace *cpuas =3D &cpu->cpu_ases[asidx]; - AddressSpaceDispatch *d =3D address_space_to_dispatch(cpuas->as); + assert(as); + AddressSpaceDispatch *d =3D address_space_to_dispatch(as); int section_index =3D index & ~TARGET_PAGE_MASK; MemoryRegionSection *ret; =20 @@ -3102,6 +3105,9 @@ static void tcg_commit(MemoryListener *listener) * That said, the listener is also called during realize, before * all of the tcg machinery for run-on is initialized: thus halt_cond. */ +// Why are these removed ?=20=20=20=20=20=20=20=20 +// cpu_reloading_memory_map(); +// tlb_flush(cpuas->cpu); if (cpu->halt_cond) { async_run_on_cpu(cpu, tcg_commit_cpu, RUN_ON_CPU_HOST_PTR(cpuas)); } else { --=20 2.51.1 --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro