Re: [PATCH v9 01/23] target/riscv: Move MISA limits to class

["Alex Bennée" <alex.bennee@linaro.org>]

Akihiko Odaki <akihiko.odaki@daynix.com> writes:

> MISA limits are common for all instances of a RISC-V CPU class so they
> are better put into class.
>
> Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
> ---
<snip>
> +static void riscv_host_cpu_init(Object *obj)
> +{
> +    CPURISCVState *env = &RISCV_CPU(obj)->env;
>      riscv_cpu_add_user_properties(obj);
>  }

You don't actually need env here, although only picked up by one
compiler:

  ../target/riscv/cpu.c: In function ‘riscv_host_cpu_init’:
  ../target/riscv/cpu.c:673:20: error: unused variable ‘env’ [-Werror=unused-variable]
    673 |     CPURISCVState *env = &RISCV_CPU(obj)->env;
        |                    ^~~
  ../target/riscv/cpu.c: At top level:
  ../target/riscv/cpu.c:2337:31: error: lvalue required as unary ‘&’ operand
   2337 |         .class_data = (void *)&(class_data_value)               \
        |                               ^
  ../target/riscv/cpu.c:2368:5: note: in expansion of macro ‘DEFINE_CPU’
   2368 |     DEFINE_CPU(TYPE_RISCV_CPU_HOST,
        |     ^~~~~~~~~~
  cc1: all warnings being treated as errors

https://gitlab.com/stsquad/qemu/-/jobs/5271601075

<snip>

-- 
Alex Bennée
Virtualisation Tech Lead @ Linaro