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Wed, 11 Oct 2023 17:06:00 +0100 (BST) References: <20231011070335.14398-1-akihiko.odaki@daynix.com> <20231011070335.14398-2-akihiko.odaki@daynix.com> User-agent: mu4e 1.11.22; emacs 29.1.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Akihiko Odaki Cc: Mikhail Tyutin , Aleksandr Anenkov , qemu-devel@nongnu.org, Philippe =?utf-8?Q?Mathieu-?= =?utf-8?Q?Daud=C3=A9?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "open list:RISC-V TCG CPUs" Subject: Re: [PATCH v9 01/23] target/riscv: Move MISA limits to class Date: Wed, 11 Oct 2023 17:04:00 +0100 In-reply-to: <20231011070335.14398-2-akihiko.odaki@daynix.com> Message-ID: <87il7dnnyv.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Akihiko Odaki writes: > MISA limits are common for all instances of a RISC-V CPU class so they > are better put into class. > > Signed-off-by: Akihiko Odaki > --- > +static void riscv_host_cpu_init(Object *obj) > +{ > + CPURISCVState *env =3D &RISCV_CPU(obj)->env; > riscv_cpu_add_user_properties(obj); > } You don't actually need env here, although only picked up by one compiler: ../target/riscv/cpu.c: In function =E2=80=98riscv_host_cpu_init=E2=80=99: ../target/riscv/cpu.c:673:20: error: unused variable =E2=80=98env=E2=80= =99 [-Werror=3Dunused-variable] 673 | CPURISCVState *env =3D &RISCV_CPU(obj)->env; | ^~~ ../target/riscv/cpu.c: At top level: ../target/riscv/cpu.c:2337:31: error: lvalue required as unary =E2=80=98&= =E2=80=99 operand 2337 | .class_data =3D (void *)&(class_data_value) = \ | ^ ../target/riscv/cpu.c:2368:5: note: in expansion of macro =E2=80=98DEFINE= _CPU=E2=80=99 2368 | DEFINE_CPU(TYPE_RISCV_CPU_HOST, | ^~~~~~~~~~ cc1: all warnings being treated as errors https://gitlab.com/stsquad/qemu/-/jobs/5271601075 --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro