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Wed, 10 May 2023 14:54:22 +0100 (BST) References: <20230506072235.597467-1-richard.henderson@linaro.org> <20230506072235.597467-28-richard.henderson@linaro.org> User-agent: mu4e 1.11.4; emacs 29.0.90 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: qemu-devel@nongnu.org, git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-arm@nongnu.org Subject: Re: [PATCH v5 27/30] tcg/ppc: Remove unused constraint J Date: Wed, 10 May 2023 14:53:30 +0100 In-reply-to: <20230506072235.597467-28-richard.henderson@linaro.org> Message-ID: <87ild05m29.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Richard Henderson writes: > Never used since its introduction. > > Fixes: 3d582c6179c ("tcg-ppc64: Rearrange integer constant constraints") > Signed-off-by: Richard Henderson > --- > tcg/ppc/tcg-target-con-str.h | 1 - > tcg/ppc/tcg-target.c.inc | 3 --- > 2 files changed, 4 deletions(-) > > diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h > index 9dcbc3df50..094613cbcb 100644 > --- a/tcg/ppc/tcg-target-con-str.h > +++ b/tcg/ppc/tcg-target-con-str.h > @@ -16,7 +16,6 @@ REGS('v', ALL_VECTOR_REGS) > * CONST(letter, TCG_CT_CONST_* bit set) > */ > CONST('I', TCG_CT_CONST_S16) > -CONST('J', TCG_CT_CONST_U16) > CONST('M', TCG_CT_CONST_MONE) > CONST('T', TCG_CT_CONST_S32) > CONST('U', TCG_CT_CONST_U32) > diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc > index 5a4ec0470a..0a14c3e997 100644 > --- a/tcg/ppc/tcg-target.c.inc > +++ b/tcg/ppc/tcg-target.c.inc > @@ -83,7 +83,6 @@ > #define SZR (TCG_TARGET_REG_BITS / 8) >=20=20 > #define TCG_CT_CONST_S16 0x100 > -#define TCG_CT_CONST_U16 0x200 Arguably you could tidy up the bit masks to make it easier to add a constraint later. But anyway: Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro