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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Peter Xu" <peterx@redhat.com>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	"Philippe Mathieu-Daudé" <philippe.mathieu-daude@linaro.org>,
	"Peter Maydell" <peter.maydell@linaro.org>
Subject: Re: should ioapic_service really be modelling cpu writes?
Date: Fri, 11 Nov 2022 14:00:28 +0000	[thread overview]
Message-ID: <87iljld1vh.fsf@linaro.org> (raw)
In-Reply-To: <99a89e48-768c-4cc2-ead4-d2014aec7d44@redhat.com>


Paolo Bonzini <pbonzini@redhat.com> writes:

> On 11/11/22 13:26, Alex Bennée wrote:
>>       if (addr > 0xfff || !index) {
>>           switch (attrs.requester_type) {
>>           }
>>           MSIMessage msi = { .address = addr, .data = val };
>>           apic_send_msi(&msi);
>>           return MEMTX_OK;
>>       }
>
>
>> which at least gets things booting properly. Does this seem like a
>> better modelling of the APIC behaviour?
>
> Yes and you don't even need the "if", just do MTRT_CPU vs everything
> else.

Can the CPU trigger MSIs by writing to this area of memory? I went for
the explicit switch for clarity but are you saying:

        if (attrs.requester_type != MTRT_CPU) {
            MSIMessage msi = { .address = addr, .data = val };
            apic_send_msi(&msi);
            return MEMTX_OK;
        } else {
            return MEMTX_ACESSS_ERROR;
        }

for the MSI range?


>
> Paolo


-- 
Alex Bennée


  reply	other threads:[~2022-11-11 14:05 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-10 17:01 should ioapic_service really be modelling cpu writes? Alex Bennée
2022-11-10 17:55 ` Alex Bennée
2022-11-10 22:42   ` Peter Xu
2022-11-11 11:08     ` Paolo Bonzini
2022-11-11 12:26     ` Alex Bennée
2022-11-11 13:14       ` Paolo Bonzini
2022-11-11 14:00         ` Alex Bennée [this message]
2022-11-11 15:57           ` Paolo Bonzini

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