From: "Alex Bennée" <alex.bennee@linaro.org>
To: Idan Horowitz <idan.horowitz@gmail.com>
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org,
richard.henderson@linaro.org, qemu-devel@nongnu.org,
pbonzini@redhat.com
Subject: Re: [PATCH 1/2] accel/tcg: Optimize jump cache flush during tlb range flush
Date: Fri, 14 Jan 2022 15:48:54 +0000 [thread overview]
Message-ID: <87ilum8gfp.fsf@linaro.org> (raw)
In-Reply-To: <20220110164754.1066025-1-idan.horowitz@gmail.com>
Idan Horowitz <idan.horowitz@gmail.com> writes:
> When the length of the range is large enough, clearing the whole cache is
> faster than iterating over the (possibly extremely large) set of pages
> contained in the range.
>
> This mimics the pre-existing similar optimization done on the flush of the
> tlb itself.
>
> Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
For multi-patch series please include a cover letter which is the parent
of all the patches. This is the default for git-send-email.
The code itself looks fine but what sort of improvements are we talking
about here? What measurements have you taken and under what conditions?
--
Alex Bennée
next prev parent reply other threads:[~2022-01-14 16:00 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-10 16:47 [PATCH 1/2] accel/tcg: Optimize jump cache flush during tlb range flush Idan Horowitz
2022-01-10 16:47 ` [PATCH 2/2] target/arm: Bail out early on 0-length tlb range invalidate Idan Horowitz
2022-01-25 22:05 ` Richard Henderson
2022-01-25 22:06 ` Peter Maydell
2022-01-25 23:34 ` Richard Henderson
2022-01-14 15:48 ` Alex Bennée [this message]
2022-01-14 16:41 ` [PATCH 1/2] accel/tcg: Optimize jump cache flush during tlb range flush Idan Horowitz
2022-01-14 20:56 ` Idan Horowitz
2022-01-25 21:55 ` Richard Henderson
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