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Wed, 28 Apr 2021 16:21:13 +0200 (CEST) From: Markus Armbruster To: Stefan Hajnoczi Subject: Re: [PATCH] hw/ide: Fix crash when plugging a piix3-ide device into the x-remote machine References: <20210416125256.2039734-1-thuth@redhat.com> <4c1c6e99-066e-f916-31dc-acb50caa5320@redhat.com> <5bbdc5d9-692e-63bb-2ad6-38a5711c4021@redhat.com> Date: Wed, 28 Apr 2021 16:21:13 +0200 In-Reply-To: (Stefan Hajnoczi's message of "Wed, 28 Apr 2021 10:15:17 +0100") Message-ID: <87im461odi.fsf@dusky.pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=armbru@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.205.24.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.22, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Elena Ufimtseva , John G Johnson , Thomas Huth , Jagannathan Raman , qemu-block@nongnu.org, Peter Maydell , John Snow , qemu-devel@nongnu.org, Paolo Bonzini , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Stefan Hajnoczi writes: > On Tue, Apr 27, 2021 at 07:54:21PM +0200, Philippe Mathieu-Daud=C3=A9 wro= te: >> On 4/27/21 7:16 PM, John Snow wrote: >> > On 4/27/21 9:54 AM, Stefan Hajnoczi wrote: >> >> I suggest fixing this at the qdev level. Make piix3-ide have a >> >> sub-device that inherits from ISA_DEVICE so it can only be instantiat= ed >> >> when there's an ISA bus. >> >> >> >> Stefan >> >=20 >> > My qdev knowledge is shaky. Does this imply that you agree with the >> > direction of Thomas's patch, or do you just mean to disagree with Phil >> > on his preferred course of action? >>=20 >> My understanding is a disagreement to both, with a 3rd direction :) >>=20 >> I agree with Stefan direction but I'm not sure (yet) that a sub-device >> is the best (long-term) solution. I guess there is a design issue with >> this device, and would like to understanding it first. >>=20 >> IIUC Stefan says the piix3-ide is both a PCI and IDE device, but QOM >> only allow a single parent. Multiple QOM inheritance is resolved as >> interfaces, but PCI/IDE qdev aren't interfaces, rather abstract objects. >> So he suggests to embed an IDE device within the PCI piix3-ide device. >>=20 >> My view is the PIIX is a chipset that share stuffs between components, >> and the IDE bus belongs to the chipset PCI root (or eventually the >> PCI-ISA bridge, function #0). The IDE function would use the IDE bus >> from its root parent as a linked property. >> My problem is currently this device is user-creatable as a Frankenstein >> single PCI function, out of its chipset. I'm not sure yet this is a >> dead end or I could work something out. > > Kevin and Paolo previously pointed out that piix3-ide is sometimes used > with the Q35 machine type. The user-creatable piix3-ide device needs to > be deprecated before it can be dropped. That's a long process that > cannot fix the current crash any time soon. > > I do support deprecating the user-creatable piix3-ide device in favor of > a proper Q35 Legacy IDE implementation. The main problem is this > involves a bunch of work and I'm not sure who would do it (the payoff is > not very high). In my opinion, letting users plug device models for PCI *functions* as if they were *devices* was a mistake. Compounding the mistake of not modelling the difference between PCI function and PCI device. The more of them we can deprecate, the better.