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X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aaron@os.amperecomputing.com, cota@braap.org, qemu-devel@nongnu.org, peter.puhov@futurewei.com, robert.foley@futurewei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > On 10/14/19 3:49 AM, Alex Benn=C3=A9e wrote: >> @@ -190,14 +211,18 @@ static uint64_t * find_counter(struct qemu_plugin_= insn *insn) >> uint32_t opcode; >> InsnClassExecCount *class =3D NULL; >> >> - /* we expect all instructions to by 32 bits for ARM */ >> - g_assert(qemu_plugin_insn_size(insn) =3D=3D 4); >> + /* >> + * We only match the first 32 bits of the instruction which is >> + * fine for most RISCs but a bit limiting for CISC architectures. >> + * They would probably benefit from a more tailored plugin. >> + * However we can fall back to individual instruction counting. >> + */ >> opcode =3D *((uint32_t *)qemu_plugin_insn_data(insn)); > > This totally ignores the endianness of the host. > I'm not keen on reading more than the number of > bytes in the insn either... I guess we can strncpy the data and ensure it is NULL terminated and use the "string" hash function instead. It depends if there are many opcode strings with NULL's in them. > > > r~ -- Alex Benn=C3=A9e