From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39148) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bG7KZ-0007mY-Lj for qemu-devel@nongnu.org; Thu, 23 Jun 2016 12:18:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bG7KU-0005rN-T0 for qemu-devel@nongnu.org; Thu, 23 Jun 2016 12:18:15 -0400 Received: from mail-wm0-x22c.google.com ([2a00:1450:400c:c09::22c]:37677) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bG7KT-0005r0-J0 for qemu-devel@nongnu.org; Thu, 23 Jun 2016 12:18:10 -0400 Received: by mail-wm0-x22c.google.com with SMTP id a66so57227705wme.0 for ; Thu, 23 Jun 2016 09:18:09 -0700 (PDT) From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <20160618040343.19517-4-bobby.prani@gmail.com> Date: Thu, 23 Jun 2016 17:18:11 +0100 Message-ID: <87inwzri9o.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [RFC v3 PATCH 03/14] tcg/aarch64: Add support for fence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Pranith Kumar Cc: Claudio Fontana , Richard Henderson , "open list:AArch64 target" , "open list:All patches CC here" , serge.fdrv@gmail.com, Claudio Fontana Pranith Kumar writes: > Cc: Claudio Fontana > Signed-off-by: Richard Henderson > Signed-off-by: Pranith Kumar > --- > tcg/aarch64/tcg-target.inc.c | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c > index 1447f7c..bc8ac9c 100644 > --- a/tcg/aarch64/tcg-target.inc.c > +++ b/tcg/aarch64/tcg-target.inc.c > @@ -372,6 +372,11 @@ typedef enum { > I3510_EOR = 0x4a000000, > I3510_EON = 0x4a200000, > I3510_ANDS = 0x6a000000, > + > + /* System instructions. */ > + DMB_ISH = 0xd50338bf, As ISH is part of the CRm encoding I wonder if this should be split into the main DMB encoding (0xd50330bf) and a separate set of CRm defines. In fact the documentation of the struct above implies you should probably have: I6260_DMB = 0xd50330bf, And then: static void tcg_out_insn_6260(TCGContext *s, AArch64Insn insn, int crm); { tcg_out32(s, insn | (crm & 0xf) << 8); } Claudio, Does this actually gain anything over doing a direct tcg_out? I guess it makes a bit more sense for more complex instruction encodings. > + DMB_LD = 0x00000100, > + DMB_ST = 0x00000200, > } AArch64Insn; > > static inline uint32_t tcg_in32(TCGContext *s) > @@ -971,6 +976,21 @@ static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl, > tcg_out_mov(s, ext, orig_rl, rl); > } > > +static inline void tcg_out_mb(TCGContext *s, TCGArg a0) > +{ > + switch (a0 & TCG_MO_ALL) { > + case TCG_MO_LD_LD: > + tcg_out32(s, DMB_ISH | DMB_LD); This would then become: tcg_out_insn(s, 6260, DMB, R_LD) > + break; > + case TCG_MO_ST_ST: > + tcg_out32(s, DMB_ISH | DMB_ST); tcg_out_insn(s, 6260, DMB, R_ST) > + break; > + default: > + tcg_out32(s, DMB_ISH | DMB_LD | DMB_ST); tcg_out_insn(s, 6260, DMB, R_LD|R_ST) > + break; > + } > +} > + > #ifdef CONFIG_SOFTMMU > /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, > * TCGMemOpIdx oi, uintptr_t ra) > @@ -1637,6 +1657,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, > tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2); > break; > > + case INDEX_op_mb: > + tcg_out_mb(s, a0); > + break; > + > case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ > case INDEX_op_mov_i64: > case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ > @@ -1761,6 +1785,7 @@ static const TCGTargetOpDef aarch64_op_defs[] = { > { INDEX_op_muluh_i64, { "r", "r", "r" } }, > { INDEX_op_mulsh_i64, { "r", "r", "r" } }, > > + { INDEX_op_mb, { } }, > { -1 }, > }; -- Alex Bennée