From: "Alex Bennée" <alex.bennee@linaro.org>
To: Julia <midnight@trainwit.ch>
Cc: "Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: Re: [PATCH 1/1] target/riscv: log guest errors when reserved bits are set in PTEs
Date: Mon, 03 Feb 2025 14:15:39 +0000 [thread overview]
Message-ID: <87jza7azck.fsf@draig.linaro.org> (raw)
In-Reply-To: <8149beba-66b1-4707-93f1-083b8bc5ece0@app.fastmail.com> (Julia's message of "Mon, 03 Feb 2025 18:12:21 +1100")
Julia <midnight@trainwit.ch> writes:
>> This happens because 'pte' is a 'target_ulong' type that, for riscv32, will be
>> interpreted as uint32_t while the FMT being used is PRIx64.
>>
>> You can fix it by using TARGET_FMT_lx instead of PRIx64:
>>
>
> I've sent a follow-up patch fixing these build errors, it builds on 32 & 64 bit on my system. Cheers
>
> As for the Signed-off-by, I'd rather not, and the contributing guide
> does not require it.
Apologies - I missed the context.
The name used with “Signed-off-by” does not need to be your legal name,
nor birth name, nor appear on any government ID. It is the identity you
choose to be known by in the community, but should not be anonymous, nor
misrepresent whom you are.
>
> Regards,
> Julia
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
next prev parent reply other threads:[~2025-02-03 14:16 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-02 5:15 [PATCH 0/1] -----BEGIN SSH SIGNATURE----- julia
2025-02-02 5:15 ` [PATCH 1/1] target/riscv: log guest errors when reserved bits are set in PTEs julia
2025-02-02 22:04 ` Daniel Henrique Barboza
2025-02-03 7:12 ` Julia
2025-02-03 14:14 ` Alex Bennée
2025-02-03 14:15 ` Alex Bennée [this message]
2025-02-03 17:29 ` Daniel Henrique Barboza
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