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Thu, 29 Jun 2023 17:28:34 +0100 (BST) References: <20230629120255.85581-1-philmd@linaro.org> <20230629120255.85581-2-philmd@linaro.org> User-agent: mu4e 1.11.7; emacs 29.0.92 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, Marcel Apfelbaum , qemu-riscv@nongnu.org, Bin Meng , Daniel Henrique Barboza , Richard Henderson , Yanan Wang , Alistair Francis , Paolo Bonzini , Weiwei Li , Palmer Dabbelt , Eduardo Habkost , Liu Zhiwei Subject: Re: [PATCH 1/2] target/riscv: Check for CF_PARALLEL instead of qemu_tcg_mttcg_enabled Date: Thu, 29 Jun 2023 17:26:59 +0100 In-reply-to: <20230629120255.85581-2-philmd@linaro.org> Message-ID: <87jzvmxmfh.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Philippe Mathieu-Daud=C3=A9 writes: > A CPU knows whether MTTCG is enabled or not because it is > reflected in its TCG flags via the CF_PARALLEL bit. > > Suggested-by: Alex Benn=C3=A9e > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/riscv/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 4035fe0e62..4dfa64af6a 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -473,7 +473,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) >=20=20 > static void rv128_base_cpu_init(Object *obj) > { > - if (qemu_tcg_mttcg_enabled()) { > + if (CPU(obj)->tcg_cflags & CF_PARALLEL) { Hmm have you checked that tcg_cpu_init_cflags() has executed by this point? > /* Missing 128-bit aligned atomics */ > error_report("128-bit RISC-V currently does not work with Multi " > "Threaded TCG. Please use: -accel tcg,thread=3Dsing= le"); Not that we can do anything about it but in linux-user we start with CF_PARALLEL unset and only set it at the point we spawn a new thread. --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro