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Thu, 29 Sep 2022 14:49:21 +0100 (BST) References: <20220925105124.82033-1-richard.henderson@linaro.org> <20220925105124.82033-15-richard.henderson@linaro.org> User-agent: mu4e 1.9.0; emacs 28.2.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Subject: Re: [PATCH v5 14/17] include/hw/core: Create struct CPUJumpCache Date: Thu, 29 Sep 2022 14:46:45 +0100 In-reply-to: <20220925105124.82033-15-richard.henderson@linaro.org> Message-ID: <87k05mz3xa.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > Wrap the bare TranslationBlock pointer into a structure. > > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Signed-off-by: Richard Henderson > --- > include/hw/core/cpu.h | 8 ++++++-- > accel/tcg/cpu-exec.c | 9 ++++++--- > accel/tcg/cputlb.c | 2 +- > accel/tcg/translate-all.c | 4 ++-- > 4 files changed, 15 insertions(+), 8 deletions(-) > > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h > index 9e47184513..ee5b75dea0 100644 > --- a/include/hw/core/cpu.h > +++ b/include/hw/core/cpu.h > @@ -232,6 +232,10 @@ struct hvf_vcpu_state; > #define TB_JMP_CACHE_BITS 12 > #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) >=20=20 > +typedef struct { > + TranslationBlock *tb; > +} CPUJumpCache; > + I don't quite follow whats going on here. I see we add vaddr pc in a later patch but I don't quite see why a cache for looking up TBs gets a sidechan value added later. Is this because the vaddr will no longer match the tb->pc? Maybe a comment on the structure is needed? > /* work queue */ >=20=20 > /* The union type allows passing of 64 bit target pointers on 32 bit > @@ -361,7 +365,7 @@ struct CPUState { > IcountDecr *icount_decr_ptr; >=20=20 > /* Accessed in parallel; all accesses must be atomic */ > - TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; > + CPUJumpCache tb_jmp_cache[TB_JMP_CACHE_SIZE]; >=20=20 > struct GDBRegisterState *gdb_regs; > int gdb_num_regs; > @@ -452,7 +456,7 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *c= pu) > unsigned int i; >=20=20 > for (i =3D 0; i < TB_JMP_CACHE_SIZE; i++) { > - qatomic_set(&cpu->tb_jmp_cache[i], NULL); > + qatomic_set(&cpu->tb_jmp_cache[i].tb, NULL); > } > } >=20=20 > diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c > index dd58a144a8..c6283d5798 100644 > --- a/accel/tcg/cpu-exec.c > +++ b/accel/tcg/cpu-exec.c > @@ -252,7 +252,7 @@ static inline TranslationBlock *tb_lookup(CPUState *c= pu, target_ulong pc, > tcg_debug_assert(!(cflags & CF_INVALID)); >=20=20 > hash =3D tb_jmp_cache_hash_func(pc); > - tb =3D qatomic_rcu_read(&cpu->tb_jmp_cache[hash]); > + tb =3D qatomic_rcu_read(&cpu->tb_jmp_cache[hash].tb); >=20=20 > if (likely(tb && > tb->pc =3D=3D pc && > @@ -266,7 +266,7 @@ static inline TranslationBlock *tb_lookup(CPUState *c= pu, target_ulong pc, > if (tb =3D=3D NULL) { > return NULL; > } > - qatomic_set(&cpu->tb_jmp_cache[hash], tb); > + qatomic_set(&cpu->tb_jmp_cache[hash].tb, tb); > return tb; > } >=20=20 > @@ -987,6 +987,8 @@ int cpu_exec(CPUState *cpu) >=20=20 > tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); > if (tb =3D=3D NULL) { > + uint32_t h; > + > mmap_lock(); > tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); > mmap_unlock(); > @@ -994,7 +996,8 @@ int cpu_exec(CPUState *cpu) > * We add the TB in the virtual pc hash table > * for the fast lookup > */ > - qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc= )], tb); > + h =3D tb_jmp_cache_hash_func(pc); > + qatomic_set(&cpu->tb_jmp_cache[h].tb, tb); > } >=20=20 > #ifndef CONFIG_USER_ONLY > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index f5e6ca2da2..fb8f3087f1 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -103,7 +103,7 @@ static void tb_jmp_cache_clear_page(CPUState *cpu, ta= rget_ulong page_addr) > unsigned int i, i0 =3D tb_jmp_cache_hash_page(page_addr); >=20=20 > for (i =3D 0; i < TB_JMP_PAGE_SIZE; i++) { > - qatomic_set(&cpu->tb_jmp_cache[i0 + i], NULL); > + qatomic_set(&cpu->tb_jmp_cache[i0 + i].tb, NULL); > } > } >=20=20 > diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c > index f429d33981..efa479ccf3 100644 > --- a/accel/tcg/translate-all.c > +++ b/accel/tcg/translate-all.c > @@ -1187,8 +1187,8 @@ static void do_tb_phys_invalidate(TranslationBlock = *tb, bool rm_from_page_list) > /* remove the TB from the hash list */ > h =3D tb_jmp_cache_hash_func(tb->pc); > CPU_FOREACH(cpu) { > - if (qatomic_read(&cpu->tb_jmp_cache[h]) =3D=3D tb) { > - qatomic_set(&cpu->tb_jmp_cache[h], NULL); > + if (qatomic_read(&cpu->tb_jmp_cache[h].tb) =3D=3D tb) { > + qatomic_set(&cpu->tb_jmp_cache[h].tb, NULL); > } > } --=20 Alex Benn=C3=A9e