From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51543) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b5xpv-00038R-Mx for qemu-devel@nongnu.org; Thu, 26 May 2016 12:08:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b5xpp-0004FK-Ui for qemu-devel@nongnu.org; Thu, 26 May 2016 12:08:38 -0400 Received: from mail-wm0-x22d.google.com ([2a00:1450:400c:c09::22d]:37825) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b5xpp-0004FF-Cq for qemu-devel@nongnu.org; Thu, 26 May 2016 12:08:33 -0400 Received: by mail-wm0-x22d.google.com with SMTP id z87so105541174wmh.0 for ; Thu, 26 May 2016 09:08:33 -0700 (PDT) References: <20160524171856.1000-1-bobby.prani@gmail.com> <20160524171856.1000-3-bobby.prani@gmail.com> <8a9b6d4e-278a-08b5-d1fb-d66e28e8e3ac@twiddle.net> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: Date: Thu, 26 May 2016 17:09:10 +0100 Message-ID: <87k2igdcnt.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [RFC PATCH 2/3] tcg: Add support for fence generation in x86 backend List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Pranith Kumar Cc: Richard Henderson , Peter Maydell , Sergey Fedorov , "open list:i386 target" Pranith Kumar writes: > Hi Richard, > > Thank you for the helpful comments. > > On Wed, May 25, 2016 at 1:35 PM, Richard Henderson wrote: >> On 05/24/2016 10:18 AM, Pranith Kumar wrote: >>> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h >>> index 92be341..93ea42e 100644 >>> --- a/tcg/i386/tcg-target.h >>> +++ b/tcg/i386/tcg-target.h >>> @@ -100,6 +100,7 @@ extern bool have_bmi1; >>> #define TCG_TARGET_HAS_muls2_i32 1 >>> #define TCG_TARGET_HAS_muluh_i32 0 >>> #define TCG_TARGET_HAS_mulsh_i32 0 >>> +#define TCG_TARGET_HAS_fence 1 >> >> >> This has to be defined for all hosts. > > OK. I will add an entry in tcg.h with default 0 and override in > individual architecture once it is implemented. > >>> @@ -347,6 +347,7 @@ static inline int >>> tcg_target_const_match(tcg_target_long val, TCGType type, >>> #define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2) >>> #define OPC_TESTL (0x85) >>> #define OPC_XCHG_ax_r32 (0x90) >>> +#define OPC_MFENCE (0xAE | P_EXT) >> >> Why define OPC_MFENCE if you're not going to use it? Of course, it's not >> exactly a complete and useful definition, so maybe just delete OPC_MFENCE. > > I want to use OPC_MFENCE instead of hard-coding the value in > tcg_out_fence(), but as you said the definition is not complete(it > currently generates only 0x0FAE). I am trying to figure out how to > generate 0x0FAEF0 using the definition. I think your going to have to just use tcg_out_fence() and the tcg_out_opc() does black magic with extra flag bits and assumes it is encoding rx registers (at least in 64 bit mode). However I would suggest a comment and maybe breakdown of the different fence types you can emit. Will pre-P4 processors never need mfences? > >> >> Also, for 32-bit you need to check for sse2 before outputting this. See >> also the existing cpuid checks in tcg_target_init and the fallback smp_mb >> definition for pre-gcc-4.4. > > OK, I'll check the current code and do something similar. > > Thanks, -- Alex Bennée