From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36663) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqRJ5-0008QY-KN for qemu-devel@nongnu.org; Tue, 10 Dec 2013 12:41:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VqRJ0-0004kA-Fa for qemu-devel@nongnu.org; Tue, 10 Dec 2013 12:41:15 -0500 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:36979 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqRJ0-0004ju-71 for qemu-devel@nongnu.org; Tue, 10 Dec 2013 12:41:10 -0500 References: <1386612744-1013-1-git-send-email-peter.maydell@linaro.org> <1386612744-1013-3-git-send-email-peter.maydell@linaro.org> <52A6271E.6050704@twiddle.net> <87wqjc6c3s.fsf@linaro.org> <52A74844.7060902@twiddle.net> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <52A74844.7060902@twiddle.net> Date: Tue, 10 Dec 2013 17:41:06 +0000 Message-ID: <87k3fc61u5.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH 2/9] target-arm: A64: add support for ldp (load pair) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: Peter Maydell , patches@linaro.org, Michael Matz , qemu-devel@nongnu.org, Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Christoffer Dall rth@twiddle.net writes: > On 12/10/2013 05:59 AM, Alex Bennée wrote: >>>> + if (extend && is_signed) { >>>> + g_assert(size < 3); >>>> + tcg_gen_ext32u_i64(dest, dest); >>>> + } >>> >>> Is it worth noticing in size==2 && !extend that is_signed can be forced false >>> to avoid the extra extension. >> >> Sorry I don't quite follow, the extension only occurs if it's an explict >> extension into a 64 bit register. Or are you talking about avoiding >> using the extension logic in the generic tcg_gen_qemu_ld_i64 code? > > It's not obvious from this patch, since its more about the later gpr loads. > I was thinking about size==4, signed, 32-bit. > > I.e. size=10, opc=11. But reading closer that's unallocated_encoding. So the > answer for this patch is "no it's not worth it". > > But looking forward through the other patches I see > >> + if (size == 3 && opc == 2) { >> + /* PRFM - prefetch */ >> + return; >> + } >> + is_store = (opc == 0); >> + is_signed = opc & (1<<1); >> + is_extended = (size < 3) && (opc & 1); > > whereas from the ARM I see > > if opc<1> == '0' then > // store or zero-extending load > else > if size == '11' then > memop = MemOp_PREFETCH; > if opc<0> == '1' then UnallocatedEncoding(); > else > // sign-extending load > memop = MemOp_LOAD; > if size == '10' && opc<0> == '1' then UnallocatedEncoding(); > > I.e. two undiagnosed unallocated_encoding. > > BTW, I find (1<<1) harder to scan here than 2, but I wasn't going to mention > that while there was nothing else in the code to fix. Yeah it's uglier than it could be, I'll see if I can make it cleaner and catch those missing unallocs. I've just finished the lpd/stp today and it's running validation overnight so I'll go through the rest of the patches tomorrow. Cheers, -- Alex Bennée QEMU/KVM Hacker for Linaro