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Mon, 24 Nov 2025 05:52:44 -0800 (PST) Received: from draig.lan ([185.126.160.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-477bf22dfc1sm197425175e9.12.2025.11.24.05.52.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 05:52:44 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 4306C5F83A; Mon, 24 Nov 2025 13:52:43 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Jim MacArthur Cc: qemu-devel@nongnu.org Subject: Re: [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 In-Reply-To: <20251120125833.123813-3-jim.macarthur@linaro.org> (Jim MacArthur's message of "Thu, 20 Nov 2025 12:54:15 +0000") References: <20251120125833.123813-1-jim.macarthur@linaro.org> <20251120125833.123813-3-jim.macarthur@linaro.org> User-Agent: mu4e 1.12.14-pre3; emacs 30.1 Date: Mon, 24 Nov 2025 13:52:43 +0000 Message-ID: <87ldjv8rmc.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Jim MacArthur writes: > This just allows read/write of three feature bits. ASID is still > ignored. Any writes to TTBR0_EL0 and TTBR1_EL0, including changing > the ASID, will still cause a complete flush of the TLB. > > Signed-off-by: Jim MacArthur I will defer to Peter on this but I'd potentially split the adding of the feature from the enabling it automatically in -cpu max. But its a minor thing given the size of the patch. Could you also update docs/system/arm/emulation.rst with the feature. Otherwise: Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro