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Fri, 9 May 2025 07:57:51 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.45.242.27]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 3F2041955F24; Fri, 9 May 2025 07:57:50 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id C312D21E66C3; Fri, 09 May 2025 09:57:47 +0200 (CEST) From: Markus Armbruster To: Peter Maydell Cc: Donald Dutile , Shameerali Kolothum Thodi , Markus Armbruster , Shameer Kolothum via , "qemu-arm@nongnu.org" , "eric.auger@redhat.com" , "jgg@nvidia.com" , "nicolinc@nvidia.com" , "berrange@redhat.com" , "nathanc@nvidia.com" , "mochs@nvidia.com" , "smostafa@google.com" , Linuxarm , "Wangzhou (B)" , jiangkunkun , Jonathan Cameron , "zhangfei.gao@linaro.org" Subject: Re: [PATCH v2 1/6] hw/arm/smmuv3: Add support to associate a PCIe RC In-Reply-To: (Peter Maydell's message of "Thu, 8 May 2025 14:57:32 +0100") References: <20250502102707.110516-1-shameerali.kolothum.thodi@huawei.com> <20250502102707.110516-2-shameerali.kolothum.thodi@huawei.com> <877c2ut0zk.fsf@pond.sub.org> <87frhglwjl.fsf@pond.sub.org> <72f9043a73294bfc9b539ae9b94836d3@huawei.com> Date: Fri, 09 May 2025 09:57:47 +0200 Message-ID: <87ldr68bd0.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.416, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Peter Maydell writes: > The problem here seems to me to be that in the hardware we're > modelling the SMMU always exists, because it's in the SoC, > but you're trying to arrange for it to be created on the > command line, via -device. > > We don't have any of these problems with the current 'virt' > board code, because we have the board code create the iommu > (if the user asks for it via the iommu machine property), > and it can wire it up to the PCI root complex as needed. So what is the motivation for creating it with -device?