* [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds
@ 2023-04-26 18:00 Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 01/13] target/arm: Move cortex sysregs into a separate file Fabiano Rosas
` (13 more replies)
0 siblings, 14 replies; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-26 18:00 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
Hi,
Some minor changes:
- new patch to move a test under CONFIG_TCG (broken on master);
- new patch to document the unsupported CPU test (Philippe);
- changed the test skip message when no KVM or TCG are present (Igor).
CI run: https://gitlab.com/farosas/qemu/-/pipelines/849926795
v10:
https://lore.kernel.org/r/20230412121829.14452-1-farosas@suse.de
v9:
https://lore.kernel.org/r/20230313151058.19645-1-farosas@suse.de
v8:
https://lore.kernel.org/r/20230309201434.10831-1-farosas@suse.de
v7 resend:
https://lore.kernel.org/r/20230228192628.26140-1-farosas@suse.de
v7:
https://lore.kernel.org/r/20230223130841.25916-1-farosas@suse.de
v6:
https://lore.kernel.org/r/20230217201150.22032-1-farosas@suse.de
v5 resend:
https://lore.kernel.org/r/20230213202927.28992-1-farosas@suse.de
v5:
https://lore.kernel.org/r/20230120184825.31626-1-farosas@suse.de
v4:
https://lore.kernel.org/r/20230119135424.5417-1-farosas@suse.de
v3:
https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de
v2:
https://lore.kernel.org/r/20230109224232.11661-1-farosas@suse.de
v1:
https://lore.kernel.org/r/20230104215835.24692-1-farosas@suse.de
Claudio Fontana (1):
target/arm: move cpu_tcg to tcg/cpu32.c
Fabiano Rosas (11):
target/arm: Move cortex sysregs into a separate file
target/arm: Remove dead code from cpu_max_set_sve_max_vq
target/arm: Extract TCG -cpu max code into a function
target/arm: Do not expose all -cpu max features to qtests
target/arm: Move 64-bit TCG CPUs into tcg/
tests/qtest: Adjust and document query-cpu-model-expansion test for
arm
tests/qtest: Fix tests when no KVM or TCG are present
tests/avocado: Pass parameters to migration test
arm/Kconfig: Always select SEMIHOSTING when TCG is present
arm/Kconfig: Do not build TCG-only boards on a KVM-only build
tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG
Philippe Mathieu-Daudé (1):
gitlab-ci: Check building KVM-only aarch64 target
.gitlab-ci.d/crossbuilds.yml | 11 +
.../custom-runners/ubuntu-22.04-aarch64.yml | 4 -
configs/devices/aarch64-softmmu/default.mak | 4 -
configs/devices/arm-softmmu/default.mak | 39 -
hw/arm/Kconfig | 43 +-
hw/arm/virt.c | 6 +-
target/arm/Kconfig | 7 +
target/arm/cortex-regs.c | 69 ++
target/arm/cpregs.h | 6 +
target/arm/cpu64.c | 702 +----------------
target/arm/internals.h | 10 +-
target/arm/meson.build | 2 +-
target/arm/{cpu_tcg.c => tcg/cpu32.c} | 72 +-
target/arm/tcg/cpu64.c | 723 ++++++++++++++++++
target/arm/tcg/meson.build | 2 +
tests/avocado/migration.py | 83 +-
tests/qtest/arm-cpu-features.c | 20 +-
tests/qtest/bios-tables-test.c | 11 +-
tests/qtest/boot-serial-test.c | 5 +
tests/qtest/meson.build | 3 +-
tests/qtest/migration-test.c | 9 +-
tests/qtest/pxe-test.c | 8 +-
tests/qtest/vmgenid-test.c | 9 +-
23 files changed, 1016 insertions(+), 832 deletions(-)
create mode 100644 target/arm/cortex-regs.c
rename target/arm/{cpu_tcg.c => tcg/cpu32.c} (93%)
create mode 100644 target/arm/tcg/cpu64.c
--
2.35.3
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v11 01/13] target/arm: Move cortex sysregs into a separate file
2023-04-26 18:00 [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
@ 2023-04-26 18:00 ` Fabiano Rosas
2023-04-28 22:41 ` Philippe Mathieu-Daudé
2023-04-26 18:00 ` [PATCH v11 02/13] target/arm: Remove dead code from cpu_max_set_sve_max_vq Fabiano Rosas
` (12 subsequent siblings)
13 siblings, 1 reply; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-26 18:00 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
The file cpu_tcg.c is about to be moved into the tcg/ directory, so
move the register definitions into a new file.
Also move the function declaration to the more appropriate cpregs.h.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
target/arm/cortex-regs.c | 69 ++++++++++++++++++++++++++++++++++++++++
target/arm/cpregs.h | 6 ++++
target/arm/cpu64.c | 1 +
target/arm/cpu_tcg.c | 59 ----------------------------------
target/arm/internals.h | 6 ----
target/arm/meson.build | 1 +
6 files changed, 77 insertions(+), 65 deletions(-)
create mode 100644 target/arm/cortex-regs.c
diff --git a/target/arm/cortex-regs.c b/target/arm/cortex-regs.c
new file mode 100644
index 0000000000..17708480e7
--- /dev/null
+++ b/target/arm/cortex-regs.c
@@ -0,0 +1,69 @@
+/*
+ * ARM Cortex-A registers
+ *
+ * This code is licensed under the GNU GPL v2 or later.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpregs.h"
+
+
+static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ ARMCPU *cpu = env_archcpu(env);
+
+ /* Number of cores is in [25:24]; otherwise we RAZ */
+ return (cpu->core_count - 1) << 24;
+}
+
+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
+ { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
+ .access = PL1_RW, .readfn = l2ctlr_read,
+ .writefn = arm_cp_write_ignore },
+ { .name = "L2CTLR",
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
+ .access = PL1_RW, .readfn = l2ctlr_read,
+ .writefn = arm_cp_write_ignore },
+ { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "L2ECTLR",
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUACTLR",
+ .cp = 15, .opc1 = 0, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUECTLR",
+ .cp = 15, .opc1 = 1, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUMERRSR",
+ .cp = 15, .opc1 = 2, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "L2MERRSR",
+ .cp = 15, .opc1 = 3, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+};
+
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
+{
+ define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+}
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 1ee64e99de..b04d344a9f 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -1071,4 +1071,10 @@ static inline bool arm_cpreg_in_idspace(const ARMCPRegInfo *ri)
ri->crn, ri->crm);
}
+#ifdef CONFIG_USER_ONLY
+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+#else
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+#endif
+
#endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 735ca54163..76891c9288 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -30,6 +30,7 @@
#include "qapi/visitor.h"
#include "hw/qdev-properties.h"
#include "internals.h"
+#include "cpregs.h"
static void aarch64_a35_initfn(Object *obj)
{
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 1911d7ec47..15aa88e40f 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -93,65 +93,6 @@ void aa32_max_features(ARMCPU *cpu)
cpu->isar.id_dfr0 = t;
}
-#ifndef CONFIG_USER_ONLY
-static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
-{
- ARMCPU *cpu = env_archcpu(env);
-
- /* Number of cores is in [25:24]; otherwise we RAZ */
- return (cpu->core_count - 1) << 24;
-}
-
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
- { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
- .access = PL1_RW, .readfn = l2ctlr_read,
- .writefn = arm_cp_write_ignore },
- { .name = "L2CTLR",
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
- .access = PL1_RW, .readfn = l2ctlr_read,
- .writefn = arm_cp_write_ignore },
- { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2ECTLR",
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUACTLR",
- .cp = 15, .opc1 = 0, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUECTLR",
- .cp = 15, .opc1 = 1, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUMERRSR",
- .cp = 15, .opc1 = 2, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2MERRSR",
- .cp = 15, .opc1 = 3, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-};
-
-void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
-{
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
-}
-#endif /* !CONFIG_USER_ONLY */
-
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index c2c70d5918..b73c540e7e 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1376,12 +1376,6 @@ uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure,
bool threadmode, bool spsel);
-#ifdef CONFIG_USER_ONLY
-static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
-#else
-void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
-#endif
-
bool el_is_in_host(CPUARMState *env, int el);
void aa32_max_features(ARMCPU *cpu);
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 6226098ad5..3469926295 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -21,6 +21,7 @@ arm_softmmu_ss.add(files(
'arch_dump.c',
'arm-powerctl.c',
'arm-qmp-cmds.c',
+ 'cortex-regs.c',
'machine.c',
'ptw.c',
))
--
2.35.3
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 02/13] target/arm: Remove dead code from cpu_max_set_sve_max_vq
2023-04-26 18:00 [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 01/13] target/arm: Move cortex sysregs into a separate file Fabiano Rosas
@ 2023-04-26 18:00 ` Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 03/13] target/arm: Extract TCG -cpu max code into a function Fabiano Rosas
` (11 subsequent siblings)
13 siblings, 0 replies; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-26 18:00 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
The sve-max-vq property has been removed from the -cpu max used with
KVM, so code under kvm_enabled in cpu_max_set_sve_max_vq is not
reachable.
Fixes: 0baa21be49 ("target/arm: Make KVM -cpu max exactly like -cpu host")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
target/arm/cpu64.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 76891c9288..fb5e1b69db 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -336,12 +336,6 @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
return;
}
- if (kvm_enabled() && !kvm_arm_sve_supported()) {
- error_setg(errp, "cannot set sve-max-vq");
- error_append_hint(errp, "SVE not supported by KVM on this host\n");
- return;
- }
-
if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
error_setg(errp, "unsupported SVE vector length");
error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
--
2.35.3
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 03/13] target/arm: Extract TCG -cpu max code into a function
2023-04-26 18:00 [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 01/13] target/arm: Move cortex sysregs into a separate file Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 02/13] target/arm: Remove dead code from cpu_max_set_sve_max_vq Fabiano Rosas
@ 2023-04-26 18:00 ` Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 04/13] target/arm: Do not expose all -cpu max features to qtests Fabiano Rosas
` (10 subsequent siblings)
13 siblings, 0 replies; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-26 18:00 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
Introduce aarch64_max_tcg_initfn that contains the TCG-only part of
-cpu max configuration. We'll need that to be able to restrict this
code to a TCG-only config in the next patches.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
target/arm/cpu64.c | 32 ++++++++++++++++++--------------
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index fb5e1b69db..e9161522b8 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -1178,27 +1178,17 @@ static void aarch64_host_initfn(Object *obj)
#endif
}
-/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
- * otherwise, a CPU with as many features enabled as our emulation supports.
- * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
+/*
+ * -cpu max: a CPU with as many features enabled as our emulation supports.
+ * The version of '-cpu max' for qemu-system-arm is defined in cpu_tcg.c;
* this only needs to handle 64 bits.
*/
-static void aarch64_max_initfn(Object *obj)
+static void aarch64_max_tcg_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
uint64_t t;
uint32_t u;
- if (kvm_enabled() || hvf_enabled()) {
- /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
- aarch64_host_initfn(obj);
- return;
- }
-
- /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
-
- aarch64_a57_initfn(obj);
-
/*
* Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
* one and try to apply errata workarounds or use impdef features we
@@ -1367,6 +1357,20 @@ static void aarch64_max_initfn(Object *obj)
qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
}
+static void aarch64_max_initfn(Object *obj)
+{
+ if (kvm_enabled() || hvf_enabled()) {
+ /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
+ aarch64_host_initfn(obj);
+ return;
+ }
+
+ /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
+
+ aarch64_a57_initfn(obj);
+ aarch64_max_tcg_initfn(obj);
+}
+
static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a35", .initfn = aarch64_a35_initfn },
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
--
2.35.3
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 04/13] target/arm: Do not expose all -cpu max features to qtests
2023-04-26 18:00 [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (2 preceding siblings ...)
2023-04-26 18:00 ` [PATCH v11 03/13] target/arm: Extract TCG -cpu max code into a function Fabiano Rosas
@ 2023-04-26 18:00 ` Fabiano Rosas
2023-04-27 9:37 ` Richard Henderson
2023-04-28 22:35 ` Philippe Mathieu-Daudé
2023-04-26 18:00 ` [PATCH v11 05/13] target/arm: Move 64-bit TCG CPUs into tcg/ Fabiano Rosas
` (9 subsequent siblings)
13 siblings, 2 replies; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-26 18:00 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
We're about to move the TCG-only -cpu max configuration code under
CONFIG_TCG. To be able to do that we need to make sure the qtests
still have some cpu configured even when no other accelerator is
available.
Delineate now what is used with TCG-only and what is also used with
qtests to make the subsequent patches cleaner.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
target/arm/cpu64.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index e9161522b8..6a6a2ece2b 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -25,6 +25,8 @@
#include "qemu/module.h"
#include "sysemu/kvm.h"
#include "sysemu/hvf.h"
+#include "sysemu/qtest.h"
+#include "sysemu/tcg.h"
#include "kvm_arm.h"
#include "hvf_arm.h"
#include "qapi/visitor.h"
@@ -1365,10 +1367,14 @@ static void aarch64_max_initfn(Object *obj)
return;
}
+ if (tcg_enabled() || qtest_enabled()) {
+ aarch64_a57_initfn(obj);
+ }
+
/* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
-
- aarch64_a57_initfn(obj);
- aarch64_max_tcg_initfn(obj);
+ if (tcg_enabled()) {
+ aarch64_max_tcg_initfn(obj);
+ }
}
static const ARMCPUInfo aarch64_cpus[] = {
--
2.35.3
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 05/13] target/arm: Move 64-bit TCG CPUs into tcg/
2023-04-26 18:00 [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (3 preceding siblings ...)
2023-04-26 18:00 ` [PATCH v11 04/13] target/arm: Do not expose all -cpu max features to qtests Fabiano Rosas
@ 2023-04-26 18:00 ` Fabiano Rosas
2023-04-28 22:38 ` Philippe Mathieu-Daudé
2023-04-26 18:00 ` [PATCH v11 06/13] tests/qtest: Adjust and document query-cpu-model-expansion test for arm Fabiano Rosas
` (8 subsequent siblings)
13 siblings, 1 reply; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-26 18:00 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
Move the 64-bit CPUs that are TCG-only:
- cortex-a35
- cortex-a55
- cortex-a72
- cortex-a76
- a64fx
- neoverse-n1
Keep the CPUs that can be used with KVM:
- cortex-a57
- cortex-a53
- max
- host
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/arm/virt.c | 6 +-
target/arm/cpu64.c | 687 +----------------------------------
target/arm/internals.h | 4 +
target/arm/tcg/cpu64.c | 723 +++++++++++++++++++++++++++++++++++++
target/arm/tcg/meson.build | 1 +
5 files changed, 735 insertions(+), 686 deletions(-)
create mode 100644 target/arm/tcg/cpu64.c
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a89d699f0b..1450a9f363 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -208,14 +208,16 @@ static const char *valid_cpus[] = {
ARM_CPU_TYPE_NAME("cortex-a7"),
#endif
ARM_CPU_TYPE_NAME("cortex-a15"),
+#ifdef CONFIG_TCG
ARM_CPU_TYPE_NAME("cortex-a35"),
- ARM_CPU_TYPE_NAME("cortex-a53"),
ARM_CPU_TYPE_NAME("cortex-a55"),
- ARM_CPU_TYPE_NAME("cortex-a57"),
ARM_CPU_TYPE_NAME("cortex-a72"),
ARM_CPU_TYPE_NAME("cortex-a76"),
ARM_CPU_TYPE_NAME("a64fx"),
ARM_CPU_TYPE_NAME("neoverse-n1"),
+#endif
+ ARM_CPU_TYPE_NAME("cortex-a53"),
+ ARM_CPU_TYPE_NAME("cortex-a57"),
ARM_CPU_TYPE_NAME("host"),
ARM_CPU_TYPE_NAME("max"),
};
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 6a6a2ece2b..6eaf8e32cf 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -34,86 +34,6 @@
#include "internals.h"
#include "cpregs.h"
-static void aarch64_a35_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,cortex-a35";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
-
- /* From B2.2 AArch64 identification registers. */
- cpu->midr = 0x411fd040;
- cpu->revidr = 0;
- cpu->ctr = 0x84448004;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
- cpu->isar.id_dfr0 = 0x03010066;
- cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_aa64pfr0 = 0x00002222;
- cpu->isar.id_aa64pfr1 = 0;
- cpu->isar.id_aa64dfr0 = 0x10305106;
- cpu->isar.id_aa64dfr1 = 0;
- cpu->isar.id_aa64isar0 = 0x00011120;
- cpu->isar.id_aa64isar1 = 0;
- cpu->isar.id_aa64mmfr0 = 0x00101122;
- cpu->isar.id_aa64mmfr1 = 0;
- cpu->clidr = 0x0a200023;
- cpu->dcz_blocksize = 4;
-
- /* From B2.4 AArch64 Virtual Memory control registers */
- cpu->reset_sctlr = 0x00c50838;
-
- /* From B2.10 AArch64 performance monitor registers */
- cpu->isar.reset_pmcr_el0 = 0x410a3000;
-
- /* From B2.29 Cache ID registers */
- cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
- cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
- cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */
-
- /* From B3.5 VGIC Type register */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
-
- /* From C6.4 Debug ID Register */
- cpu->isar.dbgdidr = 0x3516d000;
- /* From C6.5 Debug Device ID Register */
- cpu->isar.dbgdevid = 0x00110f13;
- /* From C6.6 Debug Device ID Register 1 */
- cpu->isar.dbgdevid1 = 0x2;
-
- /* From Cortex-A35 SIMD and Floating-point Support r1p0 */
- /* From 3.2 AArch32 register summary */
- cpu->reset_fpsid = 0x41034043;
-
- /* From 2.2 AArch64 register summary */
- cpu->isar.mvfr0 = 0x10110222;
- cpu->isar.mvfr1 = 0x12111111;
- cpu->isar.mvfr2 = 0x00000043;
-
- /* These values are the same with A53/A57/A72. */
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
-}
-
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
{
/*
@@ -313,41 +233,6 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
cpu->sve_vq.map = vq_map;
}
-static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- uint32_t value;
-
- /* All vector lengths are disabled when SVE is off. */
- if (!cpu_isar_feature(aa64_sve, cpu)) {
- value = 0;
- } else {
- value = cpu->sve_max_vq;
- }
- visit_type_uint32(v, name, &value, errp);
-}
-
-static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- uint32_t max_vq;
-
- if (!visit_type_uint32(v, name, &max_vq, errp)) {
- return;
- }
-
- if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
- error_setg(errp, "unsupported SVE vector length");
- error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
- ARM_MAX_VQ);
- return;
- }
-
- cpu->sve_max_vq = max_vq;
-}
-
/*
* Note that cpu_arm_{get,set}_vq cannot use the simpler
* object_property_add_bool interface because they make use of the
@@ -538,7 +423,7 @@ static void cpu_arm_get_default_vec_len(Object *obj, Visitor *v,
}
#endif
-static void aarch64_add_sve_properties(Object *obj)
+void aarch64_add_sve_properties(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
uint32_t vq;
@@ -561,7 +446,7 @@ static void aarch64_add_sve_properties(Object *obj)
#endif
}
-static void aarch64_add_sme_properties(Object *obj)
+void aarch64_add_sme_properties(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
uint32_t vq;
@@ -626,7 +511,7 @@ static Property arm_cpu_pauth_property =
static Property arm_cpu_pauth_impdef_property =
DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false);
-static void aarch64_add_pauth_properties(Object *obj)
+void aarch64_add_pauth_properties(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -647,9 +532,6 @@ static void aarch64_add_pauth_properties(Object *obj)
}
}
-static Property arm_cpu_lpa2_property =
- DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true);
-
void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
{
uint64_t t;
@@ -784,384 +666,6 @@ static void aarch64_a53_initfn(Object *obj)
define_cortex_a72_a57_a53_cp_reginfo(cpu);
}
-static void aarch64_a55_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,cortex-a55";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
-
- /* Ordered by B2.4 AArch64 registers by functional group */
- cpu->clidr = 0x82000023;
- cpu->ctr = 0x84448004; /* L1Ip = VIPT */
- cpu->dcz_blocksize = 4; /* 64 bytes */
- cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
- cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
- cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
- cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x01011121;
- cpu->isar.id_isar6 = 0x00000010;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x00021110;
- cpu->isar.id_pfr0 = 0x10010131;
- cpu->isar.id_pfr1 = 0x00011011;
- cpu->isar.id_pfr2 = 0x00000011;
- cpu->midr = 0x412FD050; /* r2p0 */
- cpu->revidr = 0;
-
- /* From B2.23 CCSIDR_EL1 */
- cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
- cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
- cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
-
- /* From B2.96 SCTLR_EL3 */
- cpu->reset_sctlr = 0x30c50838;
-
- /* From B4.45 ICH_VTR_EL2 */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
-
- cpu->isar.mvfr0 = 0x10110222;
- cpu->isar.mvfr1 = 0x13211111;
- cpu->isar.mvfr2 = 0x00000043;
-
- /* From D5.4 AArch64 PMU register summary */
- cpu->isar.reset_pmcr_el0 = 0x410b3000;
-}
-
-static void aarch64_a72_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,cortex-a72";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
- cpu->midr = 0x410fd083;
- cpu->revidr = 0x00000000;
- cpu->reset_fpsid = 0x41034080;
- cpu->isar.mvfr0 = 0x10110222;
- cpu->isar.mvfr1 = 0x12111111;
- cpu->isar.mvfr2 = 0x00000043;
- cpu->ctr = 0x8444c004;
- cpu->reset_sctlr = 0x00c50838;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
- cpu->isar.id_dfr0 = 0x03010066;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_aa64pfr0 = 0x00002222;
- cpu->isar.id_aa64dfr0 = 0x10305106;
- cpu->isar.id_aa64isar0 = 0x00011120;
- cpu->isar.id_aa64mmfr0 = 0x00001124;
- cpu->isar.dbgdidr = 0x3516d000;
- cpu->isar.dbgdevid = 0x01110f13;
- cpu->isar.dbgdevid1 = 0x2;
- cpu->isar.reset_pmcr_el0 = 0x41023000;
- cpu->clidr = 0x0a200023;
- cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
- cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
- cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
- cpu->dcz_blocksize = 4; /* 64 bytes */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
-}
-
-static void aarch64_a76_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,cortex-a76";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
-
- /* Ordered by B2.4 AArch64 registers by functional group */
- cpu->clidr = 0x82000023;
- cpu->ctr = 0x8444C004;
- cpu->dcz_blocksize = 4;
- cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
- cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x01011121;
- cpu->isar.id_isar6 = 0x00000010;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x00021110;
- cpu->isar.id_pfr0 = 0x10010131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
- cpu->isar.id_pfr2 = 0x00000011;
- cpu->midr = 0x414fd0b1; /* r4p1 */
- cpu->revidr = 0;
-
- /* From B2.18 CCSIDR_EL1 */
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
- cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
-
- /* From B2.93 SCTLR_EL3 */
- cpu->reset_sctlr = 0x30c50838;
-
- /* From B4.23 ICH_VTR_EL2 */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
-
- /* From B5.1 AdvSIMD AArch64 register summary */
- cpu->isar.mvfr0 = 0x10110222;
- cpu->isar.mvfr1 = 0x13211111;
- cpu->isar.mvfr2 = 0x00000043;
-
- /* From D5.1 AArch64 PMU register summary */
- cpu->isar.reset_pmcr_el0 = 0x410b3000;
-}
-
-static void aarch64_a64fx_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,a64fx";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
- cpu->midr = 0x461f0010;
- cpu->revidr = 0x00000000;
- cpu->ctr = 0x86668006;
- cpu->reset_sctlr = 0x30000180;
- cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
- cpu->isar.id_aa64pfr1 = 0x0000000000000000;
- cpu->isar.id_aa64dfr0 = 0x0000000010305408;
- cpu->isar.id_aa64dfr1 = 0x0000000000000000;
- cpu->id_aa64afr0 = 0x0000000000000000;
- cpu->id_aa64afr1 = 0x0000000000000000;
- cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
- cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
- cpu->isar.id_aa64isar0 = 0x0000000010211120;
- cpu->isar.id_aa64isar1 = 0x0000000000010001;
- cpu->isar.id_aa64zfr0 = 0x0000000000000000;
- cpu->clidr = 0x0000000080000023;
- cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
- cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
- cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
- cpu->dcz_blocksize = 6; /* 256 bytes */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
-
- /* The A64FX supports only 128, 256 and 512 bit vector lengths */
- aarch64_add_sve_properties(obj);
- cpu->sve_vq.supported = (1 << 0) /* 128bit */
- | (1 << 1) /* 256bit */
- | (1 << 3); /* 512bit */
-
- cpu->isar.reset_pmcr_el0 = 0x46014040;
-
- /* TODO: Add A64FX specific HPC extension registers */
-}
-
-static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
- { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
- .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- /*
- * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
- * (and in particular its system registers).
- */
- { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
- { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
- { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
- .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3,
- .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2,
- .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0,
- .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-};
-
-static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
-{
- define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo);
-}
-
-static void aarch64_neoverse_n1_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,neoverse-n1";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
-
- /* Ordered by B2.4 AArch64 registers by functional group */
- cpu->clidr = 0x82000023;
- cpu->ctr = 0x8444c004;
- cpu->dcz_blocksize = 4;
- cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
- cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x01011121;
- cpu->isar.id_isar6 = 0x00000010;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x00021110;
- cpu->isar.id_pfr0 = 0x10010131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
- cpu->isar.id_pfr2 = 0x00000011;
- cpu->midr = 0x414fd0c1; /* r4p1 */
- cpu->revidr = 0;
-
- /* From B2.23 CCSIDR_EL1 */
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
- cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
-
- /* From B2.98 SCTLR_EL3 */
- cpu->reset_sctlr = 0x30c50838;
-
- /* From B4.23 ICH_VTR_EL2 */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
-
- /* From B5.1 AdvSIMD AArch64 register summary */
- cpu->isar.mvfr0 = 0x10110222;
- cpu->isar.mvfr1 = 0x13211111;
- cpu->isar.mvfr2 = 0x00000043;
-
- /* From D5.1 AArch64 PMU register summary */
- cpu->isar.reset_pmcr_el0 = 0x410c3000;
-
- define_neoverse_n1_cp_reginfo(cpu);
-}
-
static void aarch64_host_initfn(Object *obj)
{
#if defined(CONFIG_KVM)
@@ -1180,185 +684,6 @@ static void aarch64_host_initfn(Object *obj)
#endif
}
-/*
- * -cpu max: a CPU with as many features enabled as our emulation supports.
- * The version of '-cpu max' for qemu-system-arm is defined in cpu_tcg.c;
- * this only needs to handle 64 bits.
- */
-static void aarch64_max_tcg_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- uint64_t t;
- uint32_t u;
-
- /*
- * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
- * one and try to apply errata workarounds or use impdef features we
- * don't provide.
- * An IMPLEMENTER field of 0 means "reserved for software use";
- * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
- * to see which features are present";
- * the VARIANT, PARTNUM and REVISION fields are all implementation
- * defined and we choose to define PARTNUM just in case guest
- * code needs to distinguish this QEMU CPU from other software
- * implementations, though this shouldn't be needed.
- */
- t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
- t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
- t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
- t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
- t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
- cpu->midr = t;
-
- /*
- * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS}
- * are zero.
- */
- u = cpu->clidr;
- u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0);
- u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0);
- cpu->clidr = u;
-
- t = cpu->isar.id_aa64isar0;
- t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
- t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
- t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
- t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
- t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */
- t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */
- t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */
- t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */
- t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
- t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
- t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
- cpu->isar.id_aa64isar0 = t;
-
- t = cpu->isar.id_aa64isar1;
- t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
- t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */
- t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */
- t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */
- t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */
- t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
- t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
- t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
- t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
- t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
- cpu->isar.id_aa64isar1 = t;
-
- t = cpu->isar.id_aa64pfr0;
- t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
- t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
- t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */
- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
- t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
- t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
- t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
- t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
- cpu->isar.id_aa64pfr0 = t;
-
- t = cpu->isar.id_aa64pfr1;
- t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
- t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
- /*
- * Begin with full support for MTE. This will be downgraded to MTE=0
- * during realize if the board provides no tag memory, much like
- * we do for EL2 with the virtualization=on property.
- */
- t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
- t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */
- t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
- t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
- cpu->isar.id_aa64pfr1 = t;
-
- t = cpu->isar.id_aa64mmfr0;
- t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
- t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */
- t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
- t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
- t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
- t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
- cpu->isar.id_aa64mmfr0 = t;
-
- t = cpu->isar.id_aa64mmfr1;
- t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */
- t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
- t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
- t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
- t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
- t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */
- t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
- t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */
- t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */
- cpu->isar.id_aa64mmfr1 = t;
-
- t = cpu->isar.id_aa64mmfr2;
- t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
- t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
- t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
- t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
- t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
- t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */
- t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
- t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
- t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
- t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */
- t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
- cpu->isar.id_aa64mmfr2 = t;
-
- t = cpu->isar.id_aa64zfr0;
- t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
- t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
- t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
- t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */
- t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */
- t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */
- t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
- t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
- t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
- cpu->isar.id_aa64zfr0 = t;
-
- t = cpu->isar.id_aa64dfr0;
- t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
- t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
- cpu->isar.id_aa64dfr0 = t;
-
- t = cpu->isar.id_aa64smfr0;
- t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */
- t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */
- t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */
- t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */
- t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */
- t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */
- t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */
- cpu->isar.id_aa64smfr0 = t;
-
- /* Replicate the same data to the 32-bit id registers. */
- aa32_max_features(cpu);
-
-#ifdef CONFIG_USER_ONLY
- /*
- * For usermode -cpu max we can use a larger and more efficient DCZ
- * blocksize since we don't have to follow what the hardware does.
- */
- cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
- cpu->dcz_blocksize = 7; /* 512 bytes */
-#endif
-
- cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
- cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
-
- aarch64_add_pauth_properties(obj);
- aarch64_add_sve_properties(obj);
- aarch64_add_sme_properties(obj);
- object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
- cpu_max_set_sve_max_vq, NULL, NULL);
- qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
-}
-
static void aarch64_max_initfn(Object *obj)
{
if (kvm_enabled() || hvf_enabled()) {
@@ -1378,14 +703,8 @@ static void aarch64_max_initfn(Object *obj)
}
static const ARMCPUInfo aarch64_cpus[] = {
- { .name = "cortex-a35", .initfn = aarch64_a35_initfn },
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
- { .name = "cortex-a55", .initfn = aarch64_a55_initfn },
- { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
- { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
- { .name = "a64fx", .initfn = aarch64_a64fx_initfn },
- { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
{ .name = "max", .initfn = aarch64_max_initfn },
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
{ .name = "host", .initfn = aarch64_host_initfn },
diff --git a/target/arm/internals.h b/target/arm/internals.h
index b73c540e7e..0df8f3b8bc 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1361,6 +1361,10 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
+void aarch64_max_tcg_initfn(Object *obj);
+void aarch64_add_pauth_properties(Object *obj);
+void aarch64_add_sve_properties(Object *obj);
+void aarch64_add_sme_properties(Object *obj);
#endif
/* Read the CONTROL register as the MRS instruction would. */
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
new file mode 100644
index 0000000000..646aa46ac9
--- /dev/null
+++ b/target/arm/tcg/cpu64.c
@@ -0,0 +1,723 @@
+/*
+ * QEMU AArch64 TCG CPUs
+ *
+ * Copyright (c) 2013 Linaro Ltd
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "qemu/module.h"
+#include "qapi/visitor.h"
+#include "hw/qdev-properties.h"
+#include "internals.h"
+#include "cpregs.h"
+
+static void aarch64_a35_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a35";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+ /* From B2.2 AArch64 identification registers. */
+ cpu->midr = 0x411fd040;
+ cpu->revidr = 0;
+ cpu->ctr = 0x84448004;
+ cpu->isar.id_pfr0 = 0x00000131;
+ cpu->isar.id_pfr1 = 0x00011011;
+ cpu->isar.id_dfr0 = 0x03010066;
+ cpu->id_afr0 = 0;
+ cpu->isar.id_mmfr0 = 0x10201105;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01260000;
+ cpu->isar.id_mmfr3 = 0x02102211;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232042;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00011142;
+ cpu->isar.id_isar5 = 0x00011121;
+ cpu->isar.id_aa64pfr0 = 0x00002222;
+ cpu->isar.id_aa64pfr1 = 0;
+ cpu->isar.id_aa64dfr0 = 0x10305106;
+ cpu->isar.id_aa64dfr1 = 0;
+ cpu->isar.id_aa64isar0 = 0x00011120;
+ cpu->isar.id_aa64isar1 = 0;
+ cpu->isar.id_aa64mmfr0 = 0x00101122;
+ cpu->isar.id_aa64mmfr1 = 0;
+ cpu->clidr = 0x0a200023;
+ cpu->dcz_blocksize = 4;
+
+ /* From B2.4 AArch64 Virtual Memory control registers */
+ cpu->reset_sctlr = 0x00c50838;
+
+ /* From B2.10 AArch64 performance monitor registers */
+ cpu->isar.reset_pmcr_el0 = 0x410a3000;
+
+ /* From B2.29 Cache ID registers */
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
+ cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */
+
+ /* From B3.5 VGIC Type register */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+
+ /* From C6.4 Debug ID Register */
+ cpu->isar.dbgdidr = 0x3516d000;
+ /* From C6.5 Debug Device ID Register */
+ cpu->isar.dbgdevid = 0x00110f13;
+ /* From C6.6 Debug Device ID Register 1 */
+ cpu->isar.dbgdevid1 = 0x2;
+
+ /* From Cortex-A35 SIMD and Floating-point Support r1p0 */
+ /* From 3.2 AArch32 register summary */
+ cpu->reset_fpsid = 0x41034043;
+
+ /* From 2.2 AArch64 register summary */
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x12111111;
+ cpu->isar.mvfr2 = 0x00000043;
+
+ /* These values are the same with A53/A57/A72. */
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
+}
+
+static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ uint32_t value;
+
+ /* All vector lengths are disabled when SVE is off. */
+ if (!cpu_isar_feature(aa64_sve, cpu)) {
+ value = 0;
+ } else {
+ value = cpu->sve_max_vq;
+ }
+ visit_type_uint32(v, name, &value, errp);
+}
+
+static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ uint32_t max_vq;
+
+ if (!visit_type_uint32(v, name, &max_vq, errp)) {
+ return;
+ }
+
+ if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
+ error_setg(errp, "unsupported SVE vector length");
+ error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
+ ARM_MAX_VQ);
+ return;
+ }
+
+ cpu->sve_max_vq = max_vq;
+}
+
+static Property arm_cpu_lpa2_property =
+ DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true);
+
+static void aarch64_a55_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a55";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+ /* Ordered by B2.4 AArch64 registers by functional group */
+ cpu->clidr = 0x82000023;
+ cpu->ctr = 0x84448004; /* L1Ip = VIPT */
+ cpu->dcz_blocksize = 4; /* 64 bytes */
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+ cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_dfr0 = 0x04010088;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232042;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00011142;
+ cpu->isar.id_isar5 = 0x01011121;
+ cpu->isar.id_isar6 = 0x00000010;
+ cpu->isar.id_mmfr0 = 0x10201105;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01260000;
+ cpu->isar.id_mmfr3 = 0x02122211;
+ cpu->isar.id_mmfr4 = 0x00021110;
+ cpu->isar.id_pfr0 = 0x10010131;
+ cpu->isar.id_pfr1 = 0x00011011;
+ cpu->isar.id_pfr2 = 0x00000011;
+ cpu->midr = 0x412FD050; /* r2p0 */
+ cpu->revidr = 0;
+
+ /* From B2.23 CCSIDR_EL1 */
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
+ cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
+ cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
+
+ /* From B2.96 SCTLR_EL3 */
+ cpu->reset_sctlr = 0x30c50838;
+
+ /* From B4.45 ICH_VTR_EL2 */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x13211111;
+ cpu->isar.mvfr2 = 0x00000043;
+
+ /* From D5.4 AArch64 PMU register summary */
+ cpu->isar.reset_pmcr_el0 = 0x410b3000;
+}
+
+static void aarch64_a72_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a72";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+ cpu->midr = 0x410fd083;
+ cpu->revidr = 0x00000000;
+ cpu->reset_fpsid = 0x41034080;
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x12111111;
+ cpu->isar.mvfr2 = 0x00000043;
+ cpu->ctr = 0x8444c004;
+ cpu->reset_sctlr = 0x00c50838;
+ cpu->isar.id_pfr0 = 0x00000131;
+ cpu->isar.id_pfr1 = 0x00011011;
+ cpu->isar.id_dfr0 = 0x03010066;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x10201105;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01260000;
+ cpu->isar.id_mmfr3 = 0x02102211;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232042;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00011142;
+ cpu->isar.id_isar5 = 0x00011121;
+ cpu->isar.id_aa64pfr0 = 0x00002222;
+ cpu->isar.id_aa64dfr0 = 0x10305106;
+ cpu->isar.id_aa64isar0 = 0x00011120;
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
+ cpu->isar.dbgdidr = 0x3516d000;
+ cpu->isar.dbgdevid = 0x01110f13;
+ cpu->isar.dbgdevid1 = 0x2;
+ cpu->isar.reset_pmcr_el0 = 0x41023000;
+ cpu->clidr = 0x0a200023;
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+ cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
+ cpu->dcz_blocksize = 4; /* 64 bytes */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
+}
+
+static void aarch64_a76_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a76";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+ /* Ordered by B2.4 AArch64 registers by functional group */
+ cpu->clidr = 0x82000023;
+ cpu->ctr = 0x8444C004;
+ cpu->dcz_blocksize = 4;
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_dfr0 = 0x04010088;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232042;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00010142;
+ cpu->isar.id_isar5 = 0x01011121;
+ cpu->isar.id_isar6 = 0x00000010;
+ cpu->isar.id_mmfr0 = 0x10201105;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01260000;
+ cpu->isar.id_mmfr3 = 0x02122211;
+ cpu->isar.id_mmfr4 = 0x00021110;
+ cpu->isar.id_pfr0 = 0x10010131;
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
+ cpu->isar.id_pfr2 = 0x00000011;
+ cpu->midr = 0x414fd0b1; /* r4p1 */
+ cpu->revidr = 0;
+
+ /* From B2.18 CCSIDR_EL1 */
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+ cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
+
+ /* From B2.93 SCTLR_EL3 */
+ cpu->reset_sctlr = 0x30c50838;
+
+ /* From B4.23 ICH_VTR_EL2 */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+
+ /* From B5.1 AdvSIMD AArch64 register summary */
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x13211111;
+ cpu->isar.mvfr2 = 0x00000043;
+
+ /* From D5.1 AArch64 PMU register summary */
+ cpu->isar.reset_pmcr_el0 = 0x410b3000;
+}
+
+static void aarch64_a64fx_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,a64fx";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+ cpu->midr = 0x461f0010;
+ cpu->revidr = 0x00000000;
+ cpu->ctr = 0x86668006;
+ cpu->reset_sctlr = 0x30000180;
+ cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
+ cpu->isar.id_aa64pfr1 = 0x0000000000000000;
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408;
+ cpu->isar.id_aa64dfr1 = 0x0000000000000000;
+ cpu->id_aa64afr0 = 0x0000000000000000;
+ cpu->id_aa64afr1 = 0x0000000000000000;
+ cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
+ cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
+ cpu->isar.id_aa64isar0 = 0x0000000010211120;
+ cpu->isar.id_aa64isar1 = 0x0000000000010001;
+ cpu->isar.id_aa64zfr0 = 0x0000000000000000;
+ cpu->clidr = 0x0000000080000023;
+ cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
+ cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
+ cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
+ cpu->dcz_blocksize = 6; /* 256 bytes */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+
+ /* The A64FX supports only 128, 256 and 512 bit vector lengths */
+ aarch64_add_sve_properties(obj);
+ cpu->sve_vq.supported = (1 << 0) /* 128bit */
+ | (1 << 1) /* 256bit */
+ | (1 << 3); /* 512bit */
+
+ cpu->isar.reset_pmcr_el0 = 0x46014040;
+
+ /* TODO: Add A64FX specific HPC extension registers */
+}
+
+static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
+ { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ /*
+ * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
+ * (and in particular its system registers).
+ */
+ { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
+ { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
+ { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3,
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2,
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0,
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+};
+
+static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
+{
+ define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo);
+}
+
+static void aarch64_neoverse_n1_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,neoverse-n1";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+ /* Ordered by B2.4 AArch64 registers by functional group */
+ cpu->clidr = 0x82000023;
+ cpu->ctr = 0x8444c004;
+ cpu->dcz_blocksize = 4;
+ cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
+ cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_dfr0 = 0x04010088;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232042;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00010142;
+ cpu->isar.id_isar5 = 0x01011121;
+ cpu->isar.id_isar6 = 0x00000010;
+ cpu->isar.id_mmfr0 = 0x10201105;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01260000;
+ cpu->isar.id_mmfr3 = 0x02122211;
+ cpu->isar.id_mmfr4 = 0x00021110;
+ cpu->isar.id_pfr0 = 0x10010131;
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
+ cpu->isar.id_pfr2 = 0x00000011;
+ cpu->midr = 0x414fd0c1; /* r4p1 */
+ cpu->revidr = 0;
+
+ /* From B2.23 CCSIDR_EL1 */
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+ cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
+
+ /* From B2.98 SCTLR_EL3 */
+ cpu->reset_sctlr = 0x30c50838;
+
+ /* From B4.23 ICH_VTR_EL2 */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+
+ /* From B5.1 AdvSIMD AArch64 register summary */
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x13211111;
+ cpu->isar.mvfr2 = 0x00000043;
+
+ /* From D5.1 AArch64 PMU register summary */
+ cpu->isar.reset_pmcr_el0 = 0x410c3000;
+
+ define_neoverse_n1_cp_reginfo(cpu);
+}
+
+/*
+ * -cpu max: a CPU with as many features enabled as our emulation supports.
+ * The version of '-cpu max' for qemu-system-arm is defined in cpu_tcg.c;
+ * this only needs to handle 64 bits.
+ */
+void aarch64_max_tcg_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t t;
+ uint32_t u;
+
+ /*
+ * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
+ * one and try to apply errata workarounds or use impdef features we
+ * don't provide.
+ * An IMPLEMENTER field of 0 means "reserved for software use";
+ * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
+ * to see which features are present";
+ * the VARIANT, PARTNUM and REVISION fields are all implementation
+ * defined and we choose to define PARTNUM just in case guest
+ * code needs to distinguish this QEMU CPU from other software
+ * implementations, though this shouldn't be needed.
+ */
+ t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
+ t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
+ t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
+ t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
+ t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
+ cpu->midr = t;
+
+ /*
+ * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS}
+ * are zero.
+ */
+ u = cpu->clidr;
+ u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0);
+ u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0);
+ cpu->clidr = u;
+
+ t = cpu->isar.id_aa64isar0;
+ t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
+ t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
+ t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */
+ t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */
+ t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */
+ t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
+ t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
+ t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
+ cpu->isar.id_aa64isar0 = t;
+
+ t = cpu->isar.id_aa64isar1;
+ t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
+ t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */
+ t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */
+ t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */
+ t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */
+ t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
+ t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
+ t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
+ t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
+ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
+ cpu->isar.id_aa64isar1 = t;
+
+ t = cpu->isar.id_aa64pfr0;
+ t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
+ t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
+ t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */
+ t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
+ t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
+ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
+ cpu->isar.id_aa64pfr0 = t;
+
+ t = cpu->isar.id_aa64pfr1;
+ t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
+ t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
+ /*
+ * Begin with full support for MTE. This will be downgraded to MTE=0
+ * during realize if the board provides no tag memory, much like
+ * we do for EL2 with the virtualization=on property.
+ */
+ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
+ t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */
+ t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
+ t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
+ cpu->isar.id_aa64pfr1 = t;
+
+ t = cpu->isar.id_aa64mmfr0;
+ t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
+ t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
+ cpu->isar.id_aa64mmfr0 = t;
+
+ t = cpu->isar.id_aa64mmfr1;
+ t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */
+ t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
+ t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
+ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
+ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
+ t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */
+ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
+ t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */
+ t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */
+ cpu->isar.id_aa64mmfr1 = t;
+
+ t = cpu->isar.id_aa64mmfr2;
+ t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
+ t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
+ t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
+ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
+ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
+ t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */
+ t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
+ t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
+ t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
+ t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */
+ t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
+ cpu->isar.id_aa64mmfr2 = t;
+
+ t = cpu->isar.id_aa64zfr0;
+ t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
+ t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
+ t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
+ t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */
+ t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */
+ t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */
+ t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
+ t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
+ t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
+ cpu->isar.id_aa64zfr0 = t;
+
+ t = cpu->isar.id_aa64dfr0;
+ t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
+ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
+ cpu->isar.id_aa64dfr0 = t;
+
+ t = cpu->isar.id_aa64smfr0;
+ t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */
+ t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */
+ t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */
+ t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */
+ t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */
+ t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */
+ t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */
+ cpu->isar.id_aa64smfr0 = t;
+
+ /* Replicate the same data to the 32-bit id registers. */
+ aa32_max_features(cpu);
+
+#ifdef CONFIG_USER_ONLY
+ /*
+ * For usermode -cpu max we can use a larger and more efficient DCZ
+ * blocksize since we don't have to follow what the hardware does.
+ */
+ cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
+ cpu->dcz_blocksize = 7; /* 512 bytes */
+#endif
+
+ cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
+ cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
+
+ aarch64_add_pauth_properties(obj);
+ aarch64_add_sve_properties(obj);
+ aarch64_add_sme_properties(obj);
+ object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
+ cpu_max_set_sve_max_vq, NULL, NULL);
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
+}
+
+static const ARMCPUInfo aarch64_cpus[] = {
+ { .name = "cortex-a35", .initfn = aarch64_a35_initfn },
+ { .name = "cortex-a55", .initfn = aarch64_a55_initfn },
+ { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
+ { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
+ { .name = "a64fx", .initfn = aarch64_a64fx_initfn },
+ { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
+};
+
+static void aarch64_cpu_register_types(void)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
+ aarch64_cpu_register(&aarch64_cpus[i]);
+ }
+}
+
+type_init(aarch64_cpu_register_types)
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index d27e76af6c..128f782816 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -35,6 +35,7 @@ arm_ss.add(files(
))
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
+ 'cpu64.c',
'translate-a64.c',
'translate-sve.c',
'translate-sme.c',
--
2.35.3
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 06/13] tests/qtest: Adjust and document query-cpu-model-expansion test for arm
2023-04-26 18:00 [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (4 preceding siblings ...)
2023-04-26 18:00 ` [PATCH v11 05/13] target/arm: Move 64-bit TCG CPUs into tcg/ Fabiano Rosas
@ 2023-04-26 18:00 ` Fabiano Rosas
2023-04-27 8:08 ` Thomas Huth
2023-04-27 9:39 ` Richard Henderson
2023-04-26 18:00 ` [PATCH v11 07/13] target/arm: move cpu_tcg to tcg/cpu32.c Fabiano Rosas
` (7 subsequent siblings)
13 siblings, 2 replies; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-26 18:00 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth, Laurent Vivier
We're about to move the 32-bit CPUs under CONFIG_TCG, so adjust the
query-cpu-model-expansion test to check against the cortex-a7, which
is already under CONFIG_TCG. That allows the next patch to contain
only code movement.
While here add comments clarifying what we're testing.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
tests/qtest/arm-cpu-features.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 1cb08138ad..3fc33fc24d 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -506,9 +506,23 @@ static void test_query_cpu_model_expansion_kvm(const void *data)
QDict *resp;
char *error;
- assert_error(qts, "cortex-a15",
- "We cannot guarantee the CPU type 'cortex-a15' works "
- "with KVM on this host", NULL);
+ /*
+ * When using KVM, only the 'host' and 'max' CPU models are
+ * supported. Test that we're emitting a suitable error for
+ * unsupported CPU models.
+ */
+ if (qtest_has_accel("tcg")) {
+ assert_error(qts, "cortex-a7",
+ "We cannot guarantee the CPU type 'cortex-a7' works "
+ "with KVM on this host", NULL);
+ } else {
+ /*
+ * With a KVM-only build the 32-bit CPUs are not present.
+ */
+ assert_error(qts, "cortex-a7",
+ "The CPU type 'cortex-a7' is not a "
+ "recognized ARM CPU type", NULL);
+ }
assert_has_feature_enabled(qts, "host", "aarch64");
--
2.35.3
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 07/13] target/arm: move cpu_tcg to tcg/cpu32.c
2023-04-26 18:00 [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (5 preceding siblings ...)
2023-04-26 18:00 ` [PATCH v11 06/13] tests/qtest: Adjust and document query-cpu-model-expansion test for arm Fabiano Rosas
@ 2023-04-26 18:00 ` Fabiano Rosas
2023-04-28 22:37 ` Philippe Mathieu-Daudé
2023-04-26 18:00 ` [PATCH v11 08/13] tests/qtest: Fix tests when no KVM or TCG are present Fabiano Rosas
` (6 subsequent siblings)
13 siblings, 1 reply; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-26 18:00 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth
From: Claudio Fontana <cfontana@suse.de>
move the module containing cpu models definitions
for 32bit TCG-only CPUs to tcg/ and rename it for clarity.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Thomas Huth <thuth@redhat.com>
---
hw/arm/virt.c | 2 --
target/arm/meson.build | 1 -
target/arm/{cpu_tcg.c => tcg/cpu32.c} | 13 +++----------
target/arm/tcg/cpu64.c | 2 +-
target/arm/tcg/meson.build | 1 +
5 files changed, 5 insertions(+), 14 deletions(-)
rename target/arm/{cpu_tcg.c => tcg/cpu32.c} (99%)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 1450a9f363..b99ae18501 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -206,9 +206,7 @@ static const int a15irqmap[] = {
static const char *valid_cpus[] = {
#ifdef CONFIG_TCG
ARM_CPU_TYPE_NAME("cortex-a7"),
-#endif
ARM_CPU_TYPE_NAME("cortex-a15"),
-#ifdef CONFIG_TCG
ARM_CPU_TYPE_NAME("cortex-a35"),
ARM_CPU_TYPE_NAME("cortex-a55"),
ARM_CPU_TYPE_NAME("cortex-a72"),
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 3469926295..359a649eaf 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -5,7 +5,6 @@ arm_ss.add(files(
'gdbstub.c',
'helper.c',
'vfp_helper.c',
- 'cpu_tcg.c',
))
arm_ss.add(zlib)
diff --git a/target/arm/cpu_tcg.c b/target/arm/tcg/cpu32.c
similarity index 99%
rename from target/arm/cpu_tcg.c
rename to target/arm/tcg/cpu32.c
index 15aa88e40f..47d2e8e781 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/tcg/cpu32.c
@@ -1,5 +1,5 @@
/*
- * QEMU ARM TCG CPUs.
+ * QEMU ARM TCG-only CPUs.
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@@ -10,9 +10,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
-#endif /* CONFIG_TCG */
#include "internals.h"
#include "target/arm/idau.h"
#if !defined(CONFIG_USER_ONLY)
@@ -96,7 +94,7 @@ void aa32_max_features(ARMCPU *cpu)
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+#if !defined(CONFIG_USER_ONLY)
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -120,7 +118,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
return ret;
}
-#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
+#endif /* !CONFIG_USER_ONLY */
static void arm926_initfn(Object *obj)
{
@@ -1014,7 +1012,6 @@ static void pxa270c5_initfn(Object *obj)
cpu->reset_sctlr = 0x00000078;
}
-#ifdef CONFIG_TCG
static const struct TCGCPUOps arm_v7m_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
@@ -1035,7 +1032,6 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = {
.debug_check_breakpoint = arm_debug_check_breakpoint,
#endif /* !CONFIG_USER_ONLY */
};
-#endif /* CONFIG_TCG */
static void arm_v7m_class_init(ObjectClass *oc, void *data)
{
@@ -1043,10 +1039,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
acc->info = data;
-#ifdef CONFIG_TCG
cc->tcg_ops = &arm_v7m_tcg_ops;
-#endif /* CONFIG_TCG */
-
cc->gdb_core_xml_file = "arm-m-profile.xml";
}
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 646aa46ac9..886674a443 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -525,7 +525,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
/*
* -cpu max: a CPU with as many features enabled as our emulation supports.
- * The version of '-cpu max' for qemu-system-arm is defined in cpu_tcg.c;
+ * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c;
* this only needs to handle 64 bits.
*/
void aarch64_max_tcg_initfn(Object *obj)
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index 128f782816..4d99f6dacb 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -18,6 +18,7 @@ gen = [
arm_ss.add(gen)
arm_ss.add(files(
+ 'cpu32.c',
'translate.c',
'translate-m-nocp.c',
'translate-mve.c',
--
2.35.3
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 08/13] tests/qtest: Fix tests when no KVM or TCG are present
2023-04-26 18:00 [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (6 preceding siblings ...)
2023-04-26 18:00 ` [PATCH v11 07/13] target/arm: move cpu_tcg to tcg/cpu32.c Fabiano Rosas
@ 2023-04-26 18:00 ` Fabiano Rosas
2023-04-27 9:42 ` Richard Henderson
` (2 more replies)
2023-04-26 18:00 ` [PATCH v11 09/13] tests/avocado: Pass parameters to migration test Fabiano Rosas
` (5 subsequent siblings)
13 siblings, 3 replies; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-26 18:00 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Juan Quintela, Thomas Huth, Michael S. Tsirkin, Igor Mammedov,
Ani Sinha, Laurent Vivier
It is possible to have a build with both TCG and KVM disabled due to
Xen requiring the i386 and x86_64 binaries to be present in an aarch64
host.
If we build with --disable-tcg on the aarch64 host, we will end-up
with a QEMU binary (x86) that does not support TCG nor KVM.
Skip tests that crash or hang in the above scenario. Do not include
any test cases if TCG and KVM are missing.
Make sure that calls to qtest_has_accel are placed after g_test_init
in similar fashion to commit ae4b01b349 ("tests: Ensure TAP version is
printed before other messages") to avoid TAP parsing errors.
Reviewed-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
tests/qtest/bios-tables-test.c | 11 +++++++++--
tests/qtest/boot-serial-test.c | 5 +++++
tests/qtest/migration-test.c | 9 ++++++++-
tests/qtest/pxe-test.c | 8 +++++++-
tests/qtest/vmgenid-test.c | 9 +++++++--
5 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 464f87382e..7fd88b0e9c 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -2045,8 +2045,7 @@ static void test_acpi_virt_oem_fields(void)
int main(int argc, char *argv[])
{
const char *arch = qtest_get_arch();
- const bool has_kvm = qtest_has_accel("kvm");
- const bool has_tcg = qtest_has_accel("tcg");
+ bool has_kvm, has_tcg;
char *v_env = getenv("V");
int ret;
@@ -2056,6 +2055,14 @@ int main(int argc, char *argv[])
g_test_init(&argc, &argv, NULL);
+ has_kvm = qtest_has_accel("kvm");
+ has_tcg = qtest_has_accel("tcg");
+
+ if (!has_tcg && !has_kvm) {
+ g_test_skip("No KVM or TCG accelerator available");
+ return 0;
+ }
+
if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
ret = boot_sector_init(disk);
if (ret) {
diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
index 3aef3a97a9..6dd06aeaf4 100644
--- a/tests/qtest/boot-serial-test.c
+++ b/tests/qtest/boot-serial-test.c
@@ -287,6 +287,11 @@ int main(int argc, char *argv[])
g_test_init(&argc, &argv, NULL);
+ if (!qtest_has_accel("tcg") && !qtest_has_accel("kvm")) {
+ g_test_skip("No KVM or TCG accelerator available");
+ return 0;
+ }
+
for (i = 0; tests[i].arch != NULL; i++) {
if (g_str_equal(arch, tests[i].arch) &&
qtest_has_machine(tests[i].machine)) {
diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
index 60dd53d3ec..be73ec3c06 100644
--- a/tests/qtest/migration-test.c
+++ b/tests/qtest/migration-test.c
@@ -2477,7 +2477,7 @@ static bool kvm_dirty_ring_supported(void)
int main(int argc, char **argv)
{
- bool has_kvm;
+ bool has_kvm, has_tcg;
bool has_uffd;
const char *arch;
g_autoptr(GError) err = NULL;
@@ -2486,6 +2486,13 @@ int main(int argc, char **argv)
g_test_init(&argc, &argv, NULL);
has_kvm = qtest_has_accel("kvm");
+ has_tcg = qtest_has_accel("tcg");
+
+ if (!has_tcg && !has_kvm) {
+ g_test_skip("No KVM or TCG accelerator available");
+ return 0;
+ }
+
has_uffd = ufd_version_check();
arch = qtest_get_arch();
diff --git a/tests/qtest/pxe-test.c b/tests/qtest/pxe-test.c
index 62b6eef464..e4b48225a5 100644
--- a/tests/qtest/pxe-test.c
+++ b/tests/qtest/pxe-test.c
@@ -131,11 +131,17 @@ int main(int argc, char *argv[])
int ret;
const char *arch = qtest_get_arch();
+ g_test_init(&argc, &argv, NULL);
+
+ if (!qtest_has_accel("tcg") && !qtest_has_accel("kvm")) {
+ g_test_skip("No KVM or TCG accelerator available");
+ return 0;
+ }
+
ret = boot_sector_init(disk);
if(ret)
return ret;
- g_test_init(&argc, &argv, NULL);
if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
test_batch(x86_tests, false);
diff --git a/tests/qtest/vmgenid-test.c b/tests/qtest/vmgenid-test.c
index efba76e716..324db08c7a 100644
--- a/tests/qtest/vmgenid-test.c
+++ b/tests/qtest/vmgenid-test.c
@@ -165,13 +165,18 @@ int main(int argc, char **argv)
{
int ret;
+ g_test_init(&argc, &argv, NULL);
+
+ if (!qtest_has_accel("tcg") && !qtest_has_accel("kvm")) {
+ g_test_skip("No KVM or TCG accelerator available");
+ return 0;
+ }
+
ret = boot_sector_init(disk);
if (ret) {
return ret;
}
- g_test_init(&argc, &argv, NULL);
-
qtest_add_func("/vmgenid/vmgenid/set-guid",
vmgenid_set_guid_test);
qtest_add_func("/vmgenid/vmgenid/set-guid-auto",
--
2.35.3
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 09/13] tests/avocado: Pass parameters to migration test
2023-04-26 18:00 [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (7 preceding siblings ...)
2023-04-26 18:00 ` [PATCH v11 08/13] tests/qtest: Fix tests when no KVM or TCG are present Fabiano Rosas
@ 2023-04-26 18:00 ` Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 10/13] arm/Kconfig: Always select SEMIHOSTING when TCG is present Fabiano Rosas
` (4 subsequent siblings)
13 siblings, 0 replies; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-26 18:00 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Cleber Rosa, Wainer dos Santos Moschetta, Beraldo Leal
The migration tests are currently broken for an aarch64 host because
the tests pass no 'machine' and 'cpu' options on the QEMU command
line.
Add a separate class to each architecture so that we can specify
'machine' and 'cpu' options instead of relying on defaults.
Add a skip decorator to keep the current behavior of only running
migration tests when the qemu target matches the host architecture.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
tests/avocado/migration.py | 83 +++++++++++++++++++++++++++++++++++---
1 file changed, 78 insertions(+), 5 deletions(-)
diff --git a/tests/avocado/migration.py b/tests/avocado/migration.py
index 4b25680c50..8b2ec0e3c4 100644
--- a/tests/avocado/migration.py
+++ b/tests/avocado/migration.py
@@ -11,6 +11,8 @@
import tempfile
+import os
+
from avocado_qemu import QemuSystemTest
from avocado import skipUnless
@@ -19,7 +21,7 @@
from avocado.utils.path import find_command
-class Migration(QemuSystemTest):
+class MigrationTest(QemuSystemTest):
"""
:avocado: tags=migration
"""
@@ -62,20 +64,91 @@ def _get_free_port(self):
self.cancel('Failed to find a free port')
return port
-
- def test_migration_with_tcp_localhost(self):
+ def migration_with_tcp_localhost(self):
dest_uri = 'tcp:localhost:%u' % self._get_free_port()
self.do_migrate(dest_uri)
- def test_migration_with_unix(self):
+ def migration_with_unix(self):
with tempfile.TemporaryDirectory(prefix='socket_') as socket_path:
dest_uri = 'unix:%s/qemu-test.sock' % socket_path
self.do_migrate(dest_uri)
@skipUnless(find_command('nc', default=False), "'nc' command not found")
- def test_migration_with_exec(self):
+ def migration_with_exec(self):
"""The test works for both netcat-traditional and netcat-openbsd packages."""
free_port = self._get_free_port()
dest_uri = 'exec:nc -l localhost %u' % free_port
src_uri = 'exec:nc localhost %u' % free_port
self.do_migrate(dest_uri, src_uri)
+
+
+@skipUnless('aarch64' in os.uname()[4], "host != target")
+class Aarch64(MigrationTest):
+ """
+ :avocado: tags=arch:aarch64
+ :avocado: tags=machine:virt
+ :avocado: tags=cpu:max
+ """
+
+ def test_migration_with_tcp_localhost(self):
+ self.migration_with_tcp_localhost()
+
+ def test_migration_with_unix(self):
+ self.migration_with_unix()
+
+ def test_migration_with_exec(self):
+ self.migration_with_exec()
+
+
+@skipUnless('x86_64' in os.uname()[4], "host != target")
+class X86_64(MigrationTest):
+ """
+ :avocado: tags=arch:x86_64
+ :avocado: tags=machine:pc
+ :avocado: tags=cpu:qemu64
+ """
+
+ def test_migration_with_tcp_localhost(self):
+ self.migration_with_tcp_localhost()
+
+ def test_migration_with_unix(self):
+ self.migration_with_unix()
+
+ def test_migration_with_exec(self):
+ self.migration_with_exec()
+
+
+@skipUnless('ppc64le' in os.uname()[4], "host != target")
+class PPC64(MigrationTest):
+ """
+ :avocado: tags=arch:ppc64
+ :avocado: tags=machine:pseries
+ :avocado: tags=cpu:power9_v2.0
+ """
+
+ def test_migration_with_tcp_localhost(self):
+ self.migration_with_tcp_localhost()
+
+ def test_migration_with_unix(self):
+ self.migration_with_unix()
+
+ def test_migration_with_exec(self):
+ self.migration_with_exec()
+
+
+@skipUnless('s390x' in os.uname()[4], "host != target")
+class S390X(MigrationTest):
+ """
+ :avocado: tags=arch:s390x
+ :avocado: tags=machine:s390-ccw-virtio
+ :avocado: tags=cpu:qemu
+ """
+
+ def test_migration_with_tcp_localhost(self):
+ self.migration_with_tcp_localhost()
+
+ def test_migration_with_unix(self):
+ self.migration_with_unix()
+
+ def test_migration_with_exec(self):
+ self.migration_with_exec()
--
2.35.3
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 10/13] arm/Kconfig: Always select SEMIHOSTING when TCG is present
2023-04-26 18:00 [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (8 preceding siblings ...)
2023-04-26 18:00 ` [PATCH v11 09/13] tests/avocado: Pass parameters to migration test Fabiano Rosas
@ 2023-04-26 18:00 ` Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 11/13] arm/Kconfig: Do not build TCG-only boards on a KVM-only build Fabiano Rosas
` (3 subsequent siblings)
13 siblings, 0 replies; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-26 18:00 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
We are about to enable the build without TCG, so CONFIG_SEMIHOSTING
and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in
default.mak anymore. So reflect the change in a Kconfig.
Instead of using semihosting/Kconfig, use a target-specific file, so
that the change doesn't affect other architectures which might
implement semihosting in a way compatible with KVM.
The selection from ARM_v7M needs to be removed to avoid a cycle during
parsing.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
configs/devices/arm-softmmu/default.mak | 2 --
hw/arm/Kconfig | 1 -
target/arm/Kconfig | 7 +++++++
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
index 1b49a7830c..cb3e5aea65 100644
--- a/configs/devices/arm-softmmu/default.mak
+++ b/configs/devices/arm-softmmu/default.mak
@@ -40,6 +40,4 @@ CONFIG_MICROBIT=y
CONFIG_FSL_IMX25=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
-CONFIG_SEMIHOSTING=y
-CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
CONFIG_ALLWINNER_H3=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index b53bd7f0b2..87c1a29c91 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -317,7 +317,6 @@ config ARM_V7M
# currently v7M must be included in a TCG build due to translate.c
default y if TCG && (ARM || AARCH64)
select PTIMER
- select ARM_COMPATIBLE_SEMIHOSTING
config ALLWINNER_A10
bool
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
index 3f3394a22b..39f05b6420 100644
--- a/target/arm/Kconfig
+++ b/target/arm/Kconfig
@@ -4,3 +4,10 @@ config ARM
config AARCH64
bool
select ARM
+
+# This config exists just so we can make SEMIHOSTING default when TCG
+# is selected without also changing it for other architectures.
+config ARM_SEMIHOSTING
+ bool
+ default y if TCG && ARM
+ select ARM_COMPATIBLE_SEMIHOSTING
--
2.35.3
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 11/13] arm/Kconfig: Do not build TCG-only boards on a KVM-only build
2023-04-26 18:00 [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (9 preceding siblings ...)
2023-04-26 18:00 ` [PATCH v11 10/13] arm/Kconfig: Always select SEMIHOSTING when TCG is present Fabiano Rosas
@ 2023-04-26 18:00 ` Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 12/13] tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG Fabiano Rosas
` (2 subsequent siblings)
13 siblings, 0 replies; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-26 18:00 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
Move all the CONFIG_FOO=y from default.mak into "default y if TCG"
statements in Kconfig. That way they won't be selected when
CONFIG_TCG=n.
I'm leaving CONFIG_ARM_VIRT in default.mak because it allows us to
keep the two default.mak files not empty and keep aarch64-default.mak
including arm-default.mak. That way we don't surprise anyone that's
used to altering these files.
With this change we can start building with --disable-tcg.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
configs/devices/aarch64-softmmu/default.mak | 4 --
configs/devices/arm-softmmu/default.mak | 37 ------------------
hw/arm/Kconfig | 42 ++++++++++++++++++++-
3 files changed, 41 insertions(+), 42 deletions(-)
diff --git a/configs/devices/aarch64-softmmu/default.mak b/configs/devices/aarch64-softmmu/default.mak
index cf43ac8da1..70e05a197d 100644
--- a/configs/devices/aarch64-softmmu/default.mak
+++ b/configs/devices/aarch64-softmmu/default.mak
@@ -2,7 +2,3 @@
# We support all the 32 bit boards so need all their config
include ../arm-softmmu/default.mak
-
-CONFIG_XLNX_ZYNQMP_ARM=y
-CONFIG_XLNX_VERSAL=y
-CONFIG_SBSA_REF=y
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
index cb3e5aea65..647fbce88d 100644
--- a/configs/devices/arm-softmmu/default.mak
+++ b/configs/devices/arm-softmmu/default.mak
@@ -4,40 +4,3 @@
# CONFIG_TEST_DEVICES=n
CONFIG_ARM_VIRT=y
-CONFIG_CUBIEBOARD=y
-CONFIG_EXYNOS4=y
-CONFIG_HIGHBANK=y
-CONFIG_INTEGRATOR=y
-CONFIG_FSL_IMX31=y
-CONFIG_MUSICPAL=y
-CONFIG_MUSCA=y
-CONFIG_CHEETAH=y
-CONFIG_SX1=y
-CONFIG_NSERIES=y
-CONFIG_STELLARIS=y
-CONFIG_STM32VLDISCOVERY=y
-CONFIG_REALVIEW=y
-CONFIG_VERSATILE=y
-CONFIG_VEXPRESS=y
-CONFIG_ZYNQ=y
-CONFIG_MAINSTONE=y
-CONFIG_GUMSTIX=y
-CONFIG_SPITZ=y
-CONFIG_TOSA=y
-CONFIG_Z2=y
-CONFIG_NPCM7XX=y
-CONFIG_COLLIE=y
-CONFIG_ASPEED_SOC=y
-CONFIG_NETDUINO2=y
-CONFIG_NETDUINOPLUS2=y
-CONFIG_OLIMEX_STM32_H405=y
-CONFIG_MPS2=y
-CONFIG_RASPI=y
-CONFIG_DIGIC=y
-CONFIG_SABRELITE=y
-CONFIG_EMCRAFT_SF2=y
-CONFIG_MICROBIT=y
-CONFIG_FSL_IMX25=y
-CONFIG_FSL_IMX7=y
-CONFIG_FSL_IMX6UL=y
-CONFIG_ALLWINNER_H3=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 87c1a29c91..2d7c457955 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -35,20 +35,24 @@ config ARM_VIRT
config CHEETAH
bool
+ default y if TCG && ARM
select OMAP
select TSC210X
config CUBIEBOARD
bool
+ default y if TCG && ARM
select ALLWINNER_A10
config DIGIC
bool
+ default y if TCG && ARM
select PTIMER
select PFLASH_CFI02
config EXYNOS4
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select A9MPCORE
select I2C
@@ -61,6 +65,7 @@ config EXYNOS4
config HIGHBANK
bool
+ default y if TCG && ARM
select A9MPCORE
select A15MPCORE
select AHCI
@@ -75,6 +80,7 @@ config HIGHBANK
config INTEGRATOR
bool
+ default y if TCG && ARM
select ARM_TIMER
select INTEGRATOR_DEBUG
select PL011 # UART
@@ -87,12 +93,14 @@ config INTEGRATOR
config MAINSTONE
bool
+ default y if TCG && ARM
select PXA2XX
select PFLASH_CFI01
select SMC91C111
config MUSCA
bool
+ default y if TCG && ARM
select ARMSSE
select PL011
select PL031
@@ -104,6 +112,7 @@ config MARVELL_88W8618
config MUSICPAL
bool
+ default y if TCG && ARM
select OR_IRQ
select BITBANG_I2C
select MARVELL_88W8618
@@ -114,18 +123,22 @@ config MUSICPAL
config NETDUINO2
bool
+ default y if TCG && ARM
select STM32F205_SOC
config NETDUINOPLUS2
bool
+ default y if TCG && ARM
select STM32F405_SOC
config OLIMEX_STM32_H405
bool
+ default y if TCG && ARM
select STM32F405_SOC
config NSERIES
bool
+ default y if TCG && ARM
select OMAP
select TMP105 # temperature sensor
select BLIZZARD # LCD/TV controller
@@ -158,12 +171,14 @@ config PXA2XX
config GUMSTIX
bool
+ default y if TCG && ARM
select PFLASH_CFI01
select SMC91C111
select PXA2XX
config TOSA
bool
+ default y if TCG && ARM
select ZAURUS # scoop
select MICRODRIVE
select PXA2XX
@@ -171,6 +186,7 @@ config TOSA
config SPITZ
bool
+ default y if TCG && ARM
select ADS7846 # touch-screen controller
select MAX111X # A/D converter
select WM8750 # audio codec
@@ -183,6 +199,7 @@ config SPITZ
config Z2
bool
+ default y if TCG && ARM
select PFLASH_CFI01
select WM8750
select PL011 # UART
@@ -190,6 +207,7 @@ config Z2
config REALVIEW
bool
+ default y if TCG && ARM
imply PCI_DEVICES
imply PCI_TESTDEV
imply I2C_DEVICES
@@ -218,6 +236,7 @@ config REALVIEW
config SBSA_REF
bool
+ default y if TCG && AARCH64
imply PCI_DEVICES
select AHCI
select ARM_SMMUV3
@@ -233,11 +252,13 @@ config SBSA_REF
config SABRELITE
bool
+ default y if TCG && ARM
select FSL_IMX6
select SSI_M25P80
config STELLARIS
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select ARM_V7M
select CMSDK_APB_WATCHDOG
@@ -255,6 +276,7 @@ config STELLARIS
config STM32VLDISCOVERY
bool
+ default y if TCG && ARM
select STM32F100_SOC
config STRONGARM
@@ -263,16 +285,19 @@ config STRONGARM
config COLLIE
bool
+ default y if TCG && ARM
select PFLASH_CFI01
select ZAURUS # scoop
select STRONGARM
config SX1
bool
+ default y if TCG && ARM
select OMAP
config VERSATILE
bool
+ default y if TCG && ARM
select ARM_TIMER # sp804
select PFLASH_CFI01
select LSI_SCSI_PCI
@@ -284,6 +309,7 @@ config VERSATILE
config VEXPRESS
bool
+ default y if TCG && ARM
select A9MPCORE
select A15MPCORE
select ARM_MPTIMER
@@ -299,6 +325,7 @@ config VEXPRESS
config ZYNQ
bool
+ default y if TCG && ARM
select A9MPCORE
select CADENCE # UART
select PFLASH_CFI02
@@ -315,7 +342,7 @@ config ZYNQ
config ARM_V7M
bool
# currently v7M must be included in a TCG build due to translate.c
- default y if TCG && (ARM || AARCH64)
+ default y if TCG && ARM
select PTIMER
config ALLWINNER_A10
@@ -334,6 +361,7 @@ config ALLWINNER_A10
config ALLWINNER_H3
bool
+ default y if TCG && ARM
select ALLWINNER_A10_PIT
select ALLWINNER_SUN8I_EMAC
select ALLWINNER_I2C
@@ -348,6 +376,7 @@ config ALLWINNER_H3
config RASPI
bool
+ default y if TCG && ARM
select FRAMEBUFFER
select PL011 # UART
select SDHCI
@@ -378,6 +407,7 @@ config STM32F405_SOC
config XLNX_ZYNQMP_ARM
bool
+ default y if TCG && AARCH64
select AHCI
select ARM_GIC
select CADENCE
@@ -395,6 +425,7 @@ config XLNX_ZYNQMP_ARM
config XLNX_VERSAL
bool
+ default y if TCG && AARCH64
select ARM_GIC
select PL011
select CADENCE
@@ -408,6 +439,7 @@ config XLNX_VERSAL
config NPCM7XX
bool
+ default y if TCG && ARM
select A9MPCORE
select ADM1272
select ARM_GIC
@@ -424,6 +456,7 @@ config NPCM7XX
config FSL_IMX25
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select IMX
select IMX_FEC
@@ -433,6 +466,7 @@ config FSL_IMX25
config FSL_IMX31
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select SERIAL
select IMX
@@ -453,6 +487,7 @@ config FSL_IMX6
config ASPEED_SOC
bool
+ default y if TCG && ARM
select DS1338
select FTGMAC100
select I2C
@@ -473,6 +508,7 @@ config ASPEED_SOC
config MPS2
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select ARMSSE
select LAN9118
@@ -488,6 +524,7 @@ config MPS2
config FSL_IMX7
bool
+ default y if TCG && ARM
imply PCI_DEVICES
imply TEST_DEVICES
imply I2C_DEVICES
@@ -506,6 +543,7 @@ config ARM_SMMUV3
config FSL_IMX6UL
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select A15MPCORE
select IMX
@@ -517,6 +555,7 @@ config FSL_IMX6UL
config MICROBIT
bool
+ default y if TCG && ARM
select NRF51_SOC
config NRF51_SOC
@@ -528,6 +567,7 @@ config NRF51_SOC
config EMCRAFT_SF2
bool
+ default y if TCG && ARM
select MSF2
select SSI_M25P80
--
2.35.3
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 12/13] tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG
2023-04-26 18:00 [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (10 preceding siblings ...)
2023-04-26 18:00 ` [PATCH v11 11/13] arm/Kconfig: Do not build TCG-only boards on a KVM-only build Fabiano Rosas
@ 2023-04-26 18:00 ` Fabiano Rosas
2023-04-27 7:00 ` Thomas Huth
2023-04-27 9:44 ` Richard Henderson
2023-04-26 18:00 ` [PATCH v11 13/13] gitlab-ci: Check building KVM-only aarch64 target Fabiano Rosas
2023-05-02 9:55 ` [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Peter Maydell
13 siblings, 2 replies; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-26 18:00 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth, Laurent Vivier
The test set -accel tcg, so restrict it to when TCG is present.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
tests/qtest/meson.build | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index cfc66ade6f..48cd35b5b2 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -213,7 +213,8 @@ qtests_aarch64 = \
['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \
(config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
- (config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
+ (config_all.has_key('CONFIG_TCG') and \
+ config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
['arm-cpu-features',
'numa-test',
'boot-serial-test',
--
2.35.3
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH v11 13/13] gitlab-ci: Check building KVM-only aarch64 target
2023-04-26 18:00 [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (11 preceding siblings ...)
2023-04-26 18:00 ` [PATCH v11 12/13] tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG Fabiano Rosas
@ 2023-04-26 18:00 ` Fabiano Rosas
2023-04-27 9:46 ` Richard Henderson
2023-05-02 9:55 ` [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Peter Maydell
13 siblings, 1 reply; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-26 18:00 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth, Wainer dos Santos Moschetta, Beraldo Leal
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Add a manual new job to cross-build the aarch64 target with
only the KVM accelerator enabled (in particular, no TCG).
Re-enable running the similar job on the project Aarch64
custom runner.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
---
.gitlab-ci.d/crossbuilds.yml | 11 +++++++++++
.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml | 4 ----
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml
index 61b8ac86ee..da787ea9bf 100644
--- a/.gitlab-ci.d/crossbuilds.yml
+++ b/.gitlab-ci.d/crossbuilds.yml
@@ -196,3 +196,14 @@ cross-arm64-xen-only:
IMAGE: debian-arm64-cross
ACCEL: xen
EXTRA_CONFIGURE_OPTS: --disable-tcg --disable-kvm
+
+# Similar job is run by qemu-project's custom runner by default
+cross-arm64-kvm-only:
+ extends: .cross_accel_build_job
+ needs:
+ job: arm64-debian-cross-container
+ variables:
+ QEMU_JOB_OPTIONAL: 1
+ IMAGE: debian-arm64-cross
+ ACCEL: kvm
+ EXTRA_CONFIGURE_OPTS: --disable-tcg --disable-xen --without-default-devices
diff --git a/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml b/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml
index 13e14a0f87..c61be46b82 100644
--- a/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml
+++ b/.gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml
@@ -115,11 +115,7 @@ ubuntu-22.04-aarch64-notcg:
- aarch64
rules:
- if: '$CI_PROJECT_NAMESPACE == "qemu-project" && $CI_COMMIT_BRANCH =~ /^staging/'
- when: manual
- allow_failure: true
- if: "$AARCH64_RUNNER_AVAILABLE"
- when: manual
- allow_failure: true
script:
- mkdir build
- cd build
--
2.35.3
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH v11 12/13] tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG
2023-04-26 18:00 ` [PATCH v11 12/13] tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG Fabiano Rosas
@ 2023-04-27 7:00 ` Thomas Huth
2023-04-27 9:44 ` Richard Henderson
1 sibling, 0 replies; 37+ messages in thread
From: Thomas Huth @ 2023-04-27 7:00 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Laurent Vivier
On 26/04/2023 20.00, Fabiano Rosas wrote:
> The test set -accel tcg, so restrict it to when TCG is present.
>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
> tests/qtest/meson.build | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
> index cfc66ade6f..48cd35b5b2 100644
> --- a/tests/qtest/meson.build
> +++ b/tests/qtest/meson.build
> @@ -213,7 +213,8 @@ qtests_aarch64 = \
> ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \
> (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
> (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
> - (config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
> + (config_all.has_key('CONFIG_TCG') and \
> + config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
> ['arm-cpu-features',
> 'numa-test',
> 'boot-serial-test',
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 06/13] tests/qtest: Adjust and document query-cpu-model-expansion test for arm
2023-04-26 18:00 ` [PATCH v11 06/13] tests/qtest: Adjust and document query-cpu-model-expansion test for arm Fabiano Rosas
@ 2023-04-27 8:08 ` Thomas Huth
2023-04-27 9:39 ` Richard Henderson
1 sibling, 0 replies; 37+ messages in thread
From: Thomas Huth @ 2023-04-27 8:08 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Laurent Vivier
On 26/04/2023 20.00, Fabiano Rosas wrote:
> We're about to move the 32-bit CPUs under CONFIG_TCG, so adjust the
> query-cpu-model-expansion test to check against the cortex-a7, which
> is already under CONFIG_TCG. That allows the next patch to contain
> only code movement.
>
> While here add comments clarifying what we're testing.
>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> tests/qtest/arm-cpu-features.c | 20 +++++++++++++++++---
> 1 file changed, 17 insertions(+), 3 deletions(-)
Acked-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 04/13] target/arm: Do not expose all -cpu max features to qtests
2023-04-26 18:00 ` [PATCH v11 04/13] target/arm: Do not expose all -cpu max features to qtests Fabiano Rosas
@ 2023-04-27 9:37 ` Richard Henderson
2023-04-28 22:35 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2023-04-27 9:37 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana, Eduardo Habkost,
Alexander Graf, Cornelia Huck
On 4/26/23 19:00, Fabiano Rosas wrote:
> We're about to move the TCG-only -cpu max configuration code under
> CONFIG_TCG. To be able to do that we need to make sure the qtests
> still have some cpu configured even when no other accelerator is
> available.
>
> Delineate now what is used with TCG-only and what is also used with
> qtests to make the subsequent patches cleaner.
>
> Signed-off-by: Fabiano Rosas<farosas@suse.de>
> ---
> target/arm/cpu64.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 06/13] tests/qtest: Adjust and document query-cpu-model-expansion test for arm
2023-04-26 18:00 ` [PATCH v11 06/13] tests/qtest: Adjust and document query-cpu-model-expansion test for arm Fabiano Rosas
2023-04-27 8:08 ` Thomas Huth
@ 2023-04-27 9:39 ` Richard Henderson
2023-04-27 13:16 ` Fabiano Rosas
1 sibling, 1 reply; 37+ messages in thread
From: Richard Henderson @ 2023-04-27 9:39 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana, Eduardo Habkost,
Alexander Graf, Cornelia Huck, Thomas Huth, Laurent Vivier
On 4/26/23 19:00, Fabiano Rosas wrote:
> We're about to move the 32-bit CPUs under CONFIG_TCG, so adjust the
> query-cpu-model-expansion test to check against the cortex-a7, which
> is already under CONFIG_TCG. That allows the next patch to contain
> only code movement.
>
> While here add comments clarifying what we're testing.
>
> Signed-off-by: Fabiano Rosas<farosas@suse.de>
> Suggested-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> tests/qtest/arm-cpu-features.c | 20 +++++++++++++++++---
> 1 file changed, 17 insertions(+), 3 deletions(-)
I don't see why you're changing the cpu model here.
Neither cpu will work, of course, but why change?
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 08/13] tests/qtest: Fix tests when no KVM or TCG are present
2023-04-26 18:00 ` [PATCH v11 08/13] tests/qtest: Fix tests when no KVM or TCG are present Fabiano Rosas
@ 2023-04-27 9:42 ` Richard Henderson
2023-04-27 18:41 ` Michael S. Tsirkin
2023-04-28 22:32 ` Philippe Mathieu-Daudé
2 siblings, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2023-04-27 9:42 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana, Eduardo Habkost,
Alexander Graf, Cornelia Huck, Juan Quintela, Thomas Huth,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Laurent Vivier
On 4/26/23 19:00, Fabiano Rosas wrote:
> It is possible to have a build with both TCG and KVM disabled due to
> Xen requiring the i386 and x86_64 binaries to be present in an aarch64
> host.
>
> If we build with --disable-tcg on the aarch64 host, we will end-up
> with a QEMU binary (x86) that does not support TCG nor KVM.
>
> Skip tests that crash or hang in the above scenario. Do not include
> any test cases if TCG and KVM are missing.
>
> Make sure that calls to qtest_has_accel are placed after g_test_init
> in similar fashion to commit ae4b01b349 ("tests: Ensure TAP version is
> printed before other messages") to avoid TAP parsing errors.
>
> Reviewed-by: Juan Quintela<quintela@redhat.com>
> Reviewed-by: Thomas Huth<thuth@redhat.com>
> Signed-off-by: Fabiano Rosas<farosas@suse.de>
> ---
> tests/qtest/bios-tables-test.c | 11 +++++++++--
> tests/qtest/boot-serial-test.c | 5 +++++
> tests/qtest/migration-test.c | 9 ++++++++-
> tests/qtest/pxe-test.c | 8 +++++++-
> tests/qtest/vmgenid-test.c | 9 +++++++--
> 5 files changed, 36 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 12/13] tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG
2023-04-26 18:00 ` [PATCH v11 12/13] tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG Fabiano Rosas
2023-04-27 7:00 ` Thomas Huth
@ 2023-04-27 9:44 ` Richard Henderson
1 sibling, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2023-04-27 9:44 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana, Eduardo Habkost,
Alexander Graf, Cornelia Huck, Thomas Huth, Laurent Vivier
On 4/26/23 19:00, Fabiano Rosas wrote:
> The test set -accel tcg, so restrict it to when TCG is present.
>
> Signed-off-by: Fabiano Rosas<farosas@suse.de>
> ---
> tests/qtest/meson.build | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 13/13] gitlab-ci: Check building KVM-only aarch64 target
2023-04-26 18:00 ` [PATCH v11 13/13] gitlab-ci: Check building KVM-only aarch64 target Fabiano Rosas
@ 2023-04-27 9:46 ` Richard Henderson
0 siblings, 0 replies; 37+ messages in thread
From: Richard Henderson @ 2023-04-27 9:46 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana, Eduardo Habkost,
Alexander Graf, Cornelia Huck, Thomas Huth,
Wainer dos Santos Moschetta, Beraldo Leal
On 4/26/23 19:00, Fabiano Rosas wrote:
> From: Philippe Mathieu-Daudé<philmd@linaro.org>
>
> Add a manual new job to cross-build the aarch64 target with
> only the KVM accelerator enabled (in particular, no TCG).
>
> Re-enable running the similar job on the project Aarch64
> custom runner.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> Signed-off-by: Fabiano Rosas<farosas@suse.de>
> Reviewed-by: Thomas Huth<thuth@redhat.com>
> ---
> .gitlab-ci.d/crossbuilds.yml | 11 +++++++++++
> .gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml | 4 ----
> 2 files changed, 11 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 06/13] tests/qtest: Adjust and document query-cpu-model-expansion test for arm
2023-04-27 9:39 ` Richard Henderson
@ 2023-04-27 13:16 ` Fabiano Rosas
2023-04-28 7:45 ` Richard Henderson
0 siblings, 1 reply; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-27 13:16 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana, Eduardo Habkost,
Alexander Graf, Cornelia Huck, Thomas Huth, Laurent Vivier
Richard Henderson <richard.henderson@linaro.org> writes:
> On 4/26/23 19:00, Fabiano Rosas wrote:
>> We're about to move the 32-bit CPUs under CONFIG_TCG, so adjust the
>> query-cpu-model-expansion test to check against the cortex-a7, which
>> is already under CONFIG_TCG. That allows the next patch to contain
>> only code movement.
>>
>> While here add comments clarifying what we're testing.
>>
>> Signed-off-by: Fabiano Rosas<farosas@suse.de>
>> Suggested-by: Philippe Mathieu-Daudé<philmd@linaro.org>
>> ---
>> tests/qtest/arm-cpu-features.c | 20 +++++++++++++++++---
>> 1 file changed, 17 insertions(+), 3 deletions(-)
>
> I don't see why you're changing the cpu model here.
> Neither cpu will work, of course, but why change?
>
Because there's already a patch in master that puts the cortex-a7 under
CONFIG_TCG, so I can have the whole if/else in this patch.
If I keep the cortex-a15, this change needs to go into the next patch
("move cpu_tcg to tcg/cpu32.c") which moves the rest of the 32bit cpus,
which was supposed to be only code movement.
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 08/13] tests/qtest: Fix tests when no KVM or TCG are present
2023-04-26 18:00 ` [PATCH v11 08/13] tests/qtest: Fix tests when no KVM or TCG are present Fabiano Rosas
2023-04-27 9:42 ` Richard Henderson
@ 2023-04-27 18:41 ` Michael S. Tsirkin
2023-04-28 22:32 ` Philippe Mathieu-Daudé
2 siblings, 0 replies; 37+ messages in thread
From: Michael S. Tsirkin @ 2023-04-27 18:41 UTC (permalink / raw)
To: Fabiano Rosas
Cc: qemu-devel, qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Juan Quintela, Thomas Huth, Igor Mammedov, Ani Sinha,
Laurent Vivier
On Wed, Apr 26, 2023 at 03:00:08PM -0300, Fabiano Rosas wrote:
> It is possible to have a build with both TCG and KVM disabled due to
> Xen requiring the i386 and x86_64 binaries to be present in an aarch64
> host.
>
> If we build with --disable-tcg on the aarch64 host, we will end-up
> with a QEMU binary (x86) that does not support TCG nor KVM.
>
> Skip tests that crash or hang in the above scenario. Do not include
> any test cases if TCG and KVM are missing.
>
> Make sure that calls to qtest_has_accel are placed after g_test_init
> in similar fashion to commit ae4b01b349 ("tests: Ensure TAP version is
> printed before other messages") to avoid TAP parsing errors.
>
> Reviewed-by: Juan Quintela <quintela@redhat.com>
> Reviewed-by: Thomas Huth <thuth@redhat.com>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
makes sense to me
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> tests/qtest/bios-tables-test.c | 11 +++++++++--
> tests/qtest/boot-serial-test.c | 5 +++++
> tests/qtest/migration-test.c | 9 ++++++++-
> tests/qtest/pxe-test.c | 8 +++++++-
> tests/qtest/vmgenid-test.c | 9 +++++++--
> 5 files changed, 36 insertions(+), 6 deletions(-)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index 464f87382e..7fd88b0e9c 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -2045,8 +2045,7 @@ static void test_acpi_virt_oem_fields(void)
> int main(int argc, char *argv[])
> {
> const char *arch = qtest_get_arch();
> - const bool has_kvm = qtest_has_accel("kvm");
> - const bool has_tcg = qtest_has_accel("tcg");
> + bool has_kvm, has_tcg;
> char *v_env = getenv("V");
> int ret;
>
> @@ -2056,6 +2055,14 @@ int main(int argc, char *argv[])
>
> g_test_init(&argc, &argv, NULL);
>
> + has_kvm = qtest_has_accel("kvm");
> + has_tcg = qtest_has_accel("tcg");
> +
> + if (!has_tcg && !has_kvm) {
> + g_test_skip("No KVM or TCG accelerator available");
> + return 0;
> + }
> +
> if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
> ret = boot_sector_init(disk);
> if (ret) {
> diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
> index 3aef3a97a9..6dd06aeaf4 100644
> --- a/tests/qtest/boot-serial-test.c
> +++ b/tests/qtest/boot-serial-test.c
> @@ -287,6 +287,11 @@ int main(int argc, char *argv[])
>
> g_test_init(&argc, &argv, NULL);
>
> + if (!qtest_has_accel("tcg") && !qtest_has_accel("kvm")) {
> + g_test_skip("No KVM or TCG accelerator available");
> + return 0;
> + }
> +
> for (i = 0; tests[i].arch != NULL; i++) {
> if (g_str_equal(arch, tests[i].arch) &&
> qtest_has_machine(tests[i].machine)) {
> diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
> index 60dd53d3ec..be73ec3c06 100644
> --- a/tests/qtest/migration-test.c
> +++ b/tests/qtest/migration-test.c
> @@ -2477,7 +2477,7 @@ static bool kvm_dirty_ring_supported(void)
>
> int main(int argc, char **argv)
> {
> - bool has_kvm;
> + bool has_kvm, has_tcg;
> bool has_uffd;
> const char *arch;
> g_autoptr(GError) err = NULL;
> @@ -2486,6 +2486,13 @@ int main(int argc, char **argv)
> g_test_init(&argc, &argv, NULL);
>
> has_kvm = qtest_has_accel("kvm");
> + has_tcg = qtest_has_accel("tcg");
> +
> + if (!has_tcg && !has_kvm) {
> + g_test_skip("No KVM or TCG accelerator available");
> + return 0;
> + }
> +
> has_uffd = ufd_version_check();
> arch = qtest_get_arch();
>
> diff --git a/tests/qtest/pxe-test.c b/tests/qtest/pxe-test.c
> index 62b6eef464..e4b48225a5 100644
> --- a/tests/qtest/pxe-test.c
> +++ b/tests/qtest/pxe-test.c
> @@ -131,11 +131,17 @@ int main(int argc, char *argv[])
> int ret;
> const char *arch = qtest_get_arch();
>
> + g_test_init(&argc, &argv, NULL);
> +
> + if (!qtest_has_accel("tcg") && !qtest_has_accel("kvm")) {
> + g_test_skip("No KVM or TCG accelerator available");
> + return 0;
> + }
> +
> ret = boot_sector_init(disk);
> if(ret)
> return ret;
>
> - g_test_init(&argc, &argv, NULL);
>
> if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
> test_batch(x86_tests, false);
> diff --git a/tests/qtest/vmgenid-test.c b/tests/qtest/vmgenid-test.c
> index efba76e716..324db08c7a 100644
> --- a/tests/qtest/vmgenid-test.c
> +++ b/tests/qtest/vmgenid-test.c
> @@ -165,13 +165,18 @@ int main(int argc, char **argv)
> {
> int ret;
>
> + g_test_init(&argc, &argv, NULL);
> +
> + if (!qtest_has_accel("tcg") && !qtest_has_accel("kvm")) {
> + g_test_skip("No KVM or TCG accelerator available");
> + return 0;
> + }
> +
> ret = boot_sector_init(disk);
> if (ret) {
> return ret;
> }
>
> - g_test_init(&argc, &argv, NULL);
> -
> qtest_add_func("/vmgenid/vmgenid/set-guid",
> vmgenid_set_guid_test);
> qtest_add_func("/vmgenid/vmgenid/set-guid-auto",
> --
> 2.35.3
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 06/13] tests/qtest: Adjust and document query-cpu-model-expansion test for arm
2023-04-27 13:16 ` Fabiano Rosas
@ 2023-04-28 7:45 ` Richard Henderson
2023-04-28 13:43 ` Fabiano Rosas
2023-05-02 9:46 ` Peter Maydell
0 siblings, 2 replies; 37+ messages in thread
From: Richard Henderson @ 2023-04-28 7:45 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana, Eduardo Habkost,
Alexander Graf, Cornelia Huck, Thomas Huth, Laurent Vivier
On 4/27/23 14:16, Fabiano Rosas wrote:
> Richard Henderson <richard.henderson@linaro.org> writes:
>
>> On 4/26/23 19:00, Fabiano Rosas wrote:
>>> We're about to move the 32-bit CPUs under CONFIG_TCG, so adjust the
>>> query-cpu-model-expansion test to check against the cortex-a7, which
>>> is already under CONFIG_TCG. That allows the next patch to contain
>>> only code movement.
>>>
>>> While here add comments clarifying what we're testing.
>>>
>>> Signed-off-by: Fabiano Rosas<farosas@suse.de>
>>> Suggested-by: Philippe Mathieu-Daudé<philmd@linaro.org>
>>> ---
>>> tests/qtest/arm-cpu-features.c | 20 +++++++++++++++++---
>>> 1 file changed, 17 insertions(+), 3 deletions(-)
>>
>> I don't see why you're changing the cpu model here.
>> Neither cpu will work, of course, but why change?
>>
>
> Because there's already a patch in master that puts the cortex-a7 under
> CONFIG_TCG, so I can have the whole if/else in this patch.
>
> If I keep the cortex-a15, this change needs to go into the next patch
> ("move cpu_tcg to tcg/cpu32.c") which moves the rest of the 32bit cpus,
> which was supposed to be only code movement.
Well, I still think the change to a7 is wrong.
If the two patches need to be merged to break bisection,
then so be it -- just mention that fact in the commit message.
Peter, do you agree?
r~
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 06/13] tests/qtest: Adjust and document query-cpu-model-expansion test for arm
2023-04-28 7:45 ` Richard Henderson
@ 2023-04-28 13:43 ` Fabiano Rosas
2023-05-02 9:46 ` Peter Maydell
1 sibling, 0 replies; 37+ messages in thread
From: Fabiano Rosas @ 2023-04-28 13:43 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana, Eduardo Habkost,
Alexander Graf, Cornelia Huck, Thomas Huth, Laurent Vivier
Richard Henderson <richard.henderson@linaro.org> writes:
> On 4/27/23 14:16, Fabiano Rosas wrote:
>> Richard Henderson <richard.henderson@linaro.org> writes:
>>
>>> On 4/26/23 19:00, Fabiano Rosas wrote:
>>>> We're about to move the 32-bit CPUs under CONFIG_TCG, so adjust the
>>>> query-cpu-model-expansion test to check against the cortex-a7, which
>>>> is already under CONFIG_TCG. That allows the next patch to contain
>>>> only code movement.
>>>>
>>>> While here add comments clarifying what we're testing.
>>>>
>>>> Signed-off-by: Fabiano Rosas<farosas@suse.de>
>>>> Suggested-by: Philippe Mathieu-Daudé<philmd@linaro.org>
>>>> ---
>>>> tests/qtest/arm-cpu-features.c | 20 +++++++++++++++++---
>>>> 1 file changed, 17 insertions(+), 3 deletions(-)
>>>
>>> I don't see why you're changing the cpu model here.
>>> Neither cpu will work, of course, but why change?
>>>
>>
>> Because there's already a patch in master that puts the cortex-a7 under
>> CONFIG_TCG, so I can have the whole if/else in this patch.
>>
>> If I keep the cortex-a15, this change needs to go into the next patch
>> ("move cpu_tcg to tcg/cpu32.c") which moves the rest of the 32bit cpus,
>> which was supposed to be only code movement.
>
> Well, I still think the change to a7 is wrong.
> If the two patches need to be merged to break bisection,
> then so be it -- just mention that fact in the commit message.
>
I don't get why it would be wrong. The test just needs any cpu model
that triggers the message at qmp_query_cpu_model_expansion.
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 08/13] tests/qtest: Fix tests when no KVM or TCG are present
2023-04-26 18:00 ` [PATCH v11 08/13] tests/qtest: Fix tests when no KVM or TCG are present Fabiano Rosas
2023-04-27 9:42 ` Richard Henderson
2023-04-27 18:41 ` Michael S. Tsirkin
@ 2023-04-28 22:32 ` Philippe Mathieu-Daudé
2 siblings, 0 replies; 37+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-04-28 22:32 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Richard Henderson, Alex Bennée,
Paolo Bonzini, Claudio Fontana, Eduardo Habkost, Alexander Graf,
Cornelia Huck, Juan Quintela, Thomas Huth, Michael S. Tsirkin,
Igor Mammedov, Ani Sinha, Laurent Vivier
On 26/4/23 20:00, Fabiano Rosas wrote:
> It is possible to have a build with both TCG and KVM disabled due to
> Xen requiring the i386 and x86_64 binaries to be present in an aarch64
> host.
>
> If we build with --disable-tcg on the aarch64 host, we will end-up
> with a QEMU binary (x86) that does not support TCG nor KVM.
>
> Skip tests that crash or hang in the above scenario. Do not include
> any test cases if TCG and KVM are missing.
>
> Make sure that calls to qtest_has_accel are placed after g_test_init
> in similar fashion to commit ae4b01b349 ("tests: Ensure TAP version is
> printed before other messages") to avoid TAP parsing errors.
>
> Reviewed-by: Juan Quintela <quintela@redhat.com>
> Reviewed-by: Thomas Huth <thuth@redhat.com>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
> tests/qtest/bios-tables-test.c | 11 +++++++++--
> tests/qtest/boot-serial-test.c | 5 +++++
> tests/qtest/migration-test.c | 9 ++++++++-
> tests/qtest/pxe-test.c | 8 +++++++-
> tests/qtest/vmgenid-test.c | 9 +++++++--
> 5 files changed, 36 insertions(+), 6 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 04/13] target/arm: Do not expose all -cpu max features to qtests
2023-04-26 18:00 ` [PATCH v11 04/13] target/arm: Do not expose all -cpu max features to qtests Fabiano Rosas
2023-04-27 9:37 ` Richard Henderson
@ 2023-04-28 22:35 ` Philippe Mathieu-Daudé
2023-05-02 12:23 ` Fabiano Rosas
1 sibling, 1 reply; 37+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-04-28 22:35 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Richard Henderson, Alex Bennée,
Paolo Bonzini, Claudio Fontana, Eduardo Habkost, Alexander Graf,
Cornelia Huck
On 26/4/23 20:00, Fabiano Rosas wrote:
> We're about to move the TCG-only -cpu max configuration code under
> CONFIG_TCG. To be able to do that we need to make sure the qtests
> still have some cpu configured even when no other accelerator is
> available.
>
> Delineate now what is used with TCG-only and what is also used with
> qtests to make the subsequent patches cleaner.
>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
> target/arm/cpu64.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
https://lore.kernel.org/qemu-devel/ae65d59f-5e16-24bb-aece-ccdd504fe75e@linaro.org/
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
https://lore.kernel.org/qemu-devel/4d744ee9-372b-c1f1-0d0f-be06b4b63c6f@linaro.org/
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 07/13] target/arm: move cpu_tcg to tcg/cpu32.c
2023-04-26 18:00 ` [PATCH v11 07/13] target/arm: move cpu_tcg to tcg/cpu32.c Fabiano Rosas
@ 2023-04-28 22:37 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 37+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-04-28 22:37 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Richard Henderson, Alex Bennée,
Paolo Bonzini, Claudio Fontana, Eduardo Habkost, Alexander Graf,
Cornelia Huck, Thomas Huth
On 26/4/23 20:00, Fabiano Rosas wrote:
> From: Claudio Fontana <cfontana@suse.de>
>
> move the module containing cpu models definitions
> for 32bit TCG-only CPUs to tcg/ and rename it for clarity.
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Acked-by: Thomas Huth <thuth@redhat.com>
> ---
> hw/arm/virt.c | 2 --
> target/arm/meson.build | 1 -
> target/arm/{cpu_tcg.c => tcg/cpu32.c} | 13 +++----------
> target/arm/tcg/cpu64.c | 2 +-
> target/arm/tcg/meson.build | 1 +
> 5 files changed, 5 insertions(+), 14 deletions(-)
> rename target/arm/{cpu_tcg.c => tcg/cpu32.c} (99%)
I think it took almost 3 years to get this in... :)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 05/13] target/arm: Move 64-bit TCG CPUs into tcg/
2023-04-26 18:00 ` [PATCH v11 05/13] target/arm: Move 64-bit TCG CPUs into tcg/ Fabiano Rosas
@ 2023-04-28 22:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 37+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-04-28 22:38 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Richard Henderson, Alex Bennée,
Paolo Bonzini, Claudio Fontana, Eduardo Habkost, Alexander Graf,
Cornelia Huck
On 26/4/23 20:00, Fabiano Rosas wrote:
> Move the 64-bit CPUs that are TCG-only:
> - cortex-a35
> - cortex-a55
> - cortex-a72
> - cortex-a76
> - a64fx
> - neoverse-n1
>
> Keep the CPUs that can be used with KVM:
> - cortex-a57
> - cortex-a53
> - max
> - host
>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> hw/arm/virt.c | 6 +-
> target/arm/cpu64.c | 687 +----------------------------------
> target/arm/internals.h | 4 +
> target/arm/tcg/cpu64.c | 723 +++++++++++++++++++++++++++++++++++++
> target/arm/tcg/meson.build | 1 +
> 5 files changed, 735 insertions(+), 686 deletions(-)
> create mode 100644 target/arm/tcg/cpu64.c
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 01/13] target/arm: Move cortex sysregs into a separate file
2023-04-26 18:00 ` [PATCH v11 01/13] target/arm: Move cortex sysregs into a separate file Fabiano Rosas
@ 2023-04-28 22:41 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 37+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-04-28 22:41 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Richard Henderson, Alex Bennée,
Paolo Bonzini, Claudio Fontana, Eduardo Habkost, Alexander Graf,
Cornelia Huck
On 26/4/23 20:00, Fabiano Rosas wrote:
> The file cpu_tcg.c is about to be moved into the tcg/ directory, so
> move the register definitions into a new file.
>
> Also move the function declaration to the more appropriate cpregs.h.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
> target/arm/cortex-regs.c | 69 ++++++++++++++++++++++++++++++++++++++++
Worth renaming explicitly as cortex-a_regs.c?
Otherwise,
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> target/arm/cpregs.h | 6 ++++
> target/arm/cpu64.c | 1 +
> target/arm/cpu_tcg.c | 59 ----------------------------------
> target/arm/internals.h | 6 ----
> target/arm/meson.build | 1 +
> 6 files changed, 77 insertions(+), 65 deletions(-)
> create mode 100644 target/arm/cortex-regs.c
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 06/13] tests/qtest: Adjust and document query-cpu-model-expansion test for arm
2023-04-28 7:45 ` Richard Henderson
2023-04-28 13:43 ` Fabiano Rosas
@ 2023-05-02 9:46 ` Peter Maydell
1 sibling, 0 replies; 37+ messages in thread
From: Peter Maydell @ 2023-05-02 9:46 UTC (permalink / raw)
To: Richard Henderson
Cc: Fabiano Rosas, qemu-devel, qemu-arm, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana, Eduardo Habkost,
Alexander Graf, Cornelia Huck, Thomas Huth, Laurent Vivier
On Fri, 28 Apr 2023 at 08:45, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/27/23 14:16, Fabiano Rosas wrote:
> > Richard Henderson <richard.henderson@linaro.org> writes:
> >
> >> On 4/26/23 19:00, Fabiano Rosas wrote:
> >>> We're about to move the 32-bit CPUs under CONFIG_TCG, so adjust the
> >>> query-cpu-model-expansion test to check against the cortex-a7, which
> >>> is already under CONFIG_TCG. That allows the next patch to contain
> >>> only code movement.
> >>>
> >>> While here add comments clarifying what we're testing.
> >>>
> >>> Signed-off-by: Fabiano Rosas<farosas@suse.de>
> >>> Suggested-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> >>> ---
> >>> tests/qtest/arm-cpu-features.c | 20 +++++++++++++++++---
> >>> 1 file changed, 17 insertions(+), 3 deletions(-)
> >>
> >> I don't see why you're changing the cpu model here.
> >> Neither cpu will work, of course, but why change?
> >>
> >
> > Because there's already a patch in master that puts the cortex-a7 under
> > CONFIG_TCG, so I can have the whole if/else in this patch.
> >
> > If I keep the cortex-a15, this change needs to go into the next patch
> > ("move cpu_tcg to tcg/cpu32.c") which moves the rest of the 32bit cpus,
> > which was supposed to be only code movement.
>
> Well, I still think the change to a7 is wrong.
> If the two patches need to be merged to break bisection,
> then so be it -- just mention that fact in the commit message.
>
> Peter, do you agree?
I see your point, but on the other hand this is only test
code, and the situation it's checking is a rather
uninteresting one anyway. So given that this series is
already on v11 and it's an awkward one to have to keep
rebasing, I'd rather take it as-is than ask for a reroll.
thanks
-- PMM
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds
2023-04-26 18:00 [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (12 preceding siblings ...)
2023-04-26 18:00 ` [PATCH v11 13/13] gitlab-ci: Check building KVM-only aarch64 target Fabiano Rosas
@ 2023-05-02 9:55 ` Peter Maydell
2023-05-02 14:51 ` Peter Maydell
13 siblings, 1 reply; 37+ messages in thread
From: Peter Maydell @ 2023-05-02 9:55 UTC (permalink / raw)
To: Fabiano Rosas
Cc: qemu-devel, qemu-arm, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
On Wed, 26 Apr 2023 at 19:00, Fabiano Rosas <farosas@suse.de> wrote:
>
> Hi,
>
> Some minor changes:
>
> - new patch to move a test under CONFIG_TCG (broken on master);
> - new patch to document the unsupported CPU test (Philippe);
> - changed the test skip message when no KVM or TCG are present (Igor).
Applied to target-arm.next; thanks for your persistence in
working through the many versions of this patchset.
-- PMM
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 04/13] target/arm: Do not expose all -cpu max features to qtests
2023-04-28 22:35 ` Philippe Mathieu-Daudé
@ 2023-05-02 12:23 ` Fabiano Rosas
0 siblings, 0 replies; 37+ messages in thread
From: Fabiano Rosas @ 2023-05-02 12:23 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-arm, Peter Maydell, Richard Henderson, Alex Bennée,
Paolo Bonzini, Claudio Fontana, Eduardo Habkost, Alexander Graf,
Cornelia Huck
Philippe Mathieu-Daudé <philmd@linaro.org> writes:
> On 26/4/23 20:00, Fabiano Rosas wrote:
>> We're about to move the TCG-only -cpu max configuration code under
>> CONFIG_TCG. To be able to do that we need to make sure the qtests
>> still have some cpu configured even when no other accelerator is
>> available.
>>
>> Delineate now what is used with TCG-only and what is also used with
>> qtests to make the subsequent patches cleaner.
>>
>> Signed-off-by: Fabiano Rosas <farosas@suse.de>
>> ---
>> target/arm/cpu64.c | 12 +++++++++---
>> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> https://lore.kernel.org/qemu-devel/ae65d59f-5e16-24bb-aece-ccdd504fe75e@linaro.org/
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>
> https://lore.kernel.org/qemu-devel/4d744ee9-372b-c1f1-0d0f-be06b4b63c6f@linaro.org/
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Ah, thank you! The 'b4 trailers' must have failed and I didn't notice.
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds
2023-05-02 9:55 ` [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Peter Maydell
@ 2023-05-02 14:51 ` Peter Maydell
2023-05-02 16:07 ` Peter Maydell
0 siblings, 1 reply; 37+ messages in thread
From: Peter Maydell @ 2023-05-02 14:51 UTC (permalink / raw)
To: Fabiano Rosas
Cc: qemu-devel, qemu-arm, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
On Tue, 2 May 2023 at 10:55, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Wed, 26 Apr 2023 at 19:00, Fabiano Rosas <farosas@suse.de> wrote:
> >
> > Hi,
> >
> > Some minor changes:
> >
> > - new patch to move a test under CONFIG_TCG (broken on master);
> > - new patch to document the unsupported CPU test (Philippe);
> > - changed the test skip message when no KVM or TCG are present (Igor).
>
> Applied to target-arm.next; thanks for your persistence in
> working through the many versions of this patchset.
Update: I had to drop "gitlab-ci: Check building KVM-only aarch64 target"
because it enables a CI job that fails on our aarch64 runner
(because it wants to run tests using KVM but that machine
isn't configured to allow the runner to use KVM).
thanks
-- PMM
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds
2023-05-02 14:51 ` Peter Maydell
@ 2023-05-02 16:07 ` Peter Maydell
2023-05-02 16:23 ` Fabiano Rosas
0 siblings, 1 reply; 37+ messages in thread
From: Peter Maydell @ 2023-05-02 16:07 UTC (permalink / raw)
To: Fabiano Rosas
Cc: qemu-devel, qemu-arm, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée
On Tue, 2 May 2023 at 15:51, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Tue, 2 May 2023 at 10:55, Peter Maydell <peter.maydell@linaro.org> wrote:
> >
> > On Wed, 26 Apr 2023 at 19:00, Fabiano Rosas <farosas@suse.de> wrote:
> > >
> > > Hi,
> > >
> > > Some minor changes:
> > >
> > > - new patch to move a test under CONFIG_TCG (broken on master);
> > > - new patch to document the unsupported CPU test (Philippe);
> > > - changed the test skip message when no KVM or TCG are present (Igor).
> >
> > Applied to target-arm.next; thanks for your persistence in
> > working through the many versions of this patchset.
>
> Update: I had to drop "gitlab-ci: Check building KVM-only aarch64 target"
> because it enables a CI job that fails on our aarch64 runner
> (because it wants to run tests using KVM but that machine
> isn't configured to allow the runner to use KVM).
We fixed the runner config, but the CI still fails on that notcg
job because it is trying to run tests that explicitly use
'-accel tcg':
https://gitlab.com/qemu-project/qemu/-/jobs/4212850809#L3595
Something is weird here, because we built without TCG support
on an aarch64 host but we still got qemu-system-i386
and qemu-system-x86_64 binaries, which then don't work
and cause the tests to fail...
-- PMM
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds
2023-05-02 16:07 ` Peter Maydell
@ 2023-05-02 16:23 ` Fabiano Rosas
2023-05-02 17:11 ` Fabiano Rosas
0 siblings, 1 reply; 37+ messages in thread
From: Fabiano Rosas @ 2023-05-02 16:23 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-devel, qemu-arm, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée
Peter Maydell <peter.maydell@linaro.org> writes:
> On Tue, 2 May 2023 at 15:51, Peter Maydell <peter.maydell@linaro.org> wrote:
>>
>> On Tue, 2 May 2023 at 10:55, Peter Maydell <peter.maydell@linaro.org> wrote:
>> >
>> > On Wed, 26 Apr 2023 at 19:00, Fabiano Rosas <farosas@suse.de> wrote:
>> > >
>> > > Hi,
>> > >
>> > > Some minor changes:
>> > >
>> > > - new patch to move a test under CONFIG_TCG (broken on master);
>> > > - new patch to document the unsupported CPU test (Philippe);
>> > > - changed the test skip message when no KVM or TCG are present (Igor).
>> >
>> > Applied to target-arm.next; thanks for your persistence in
>> > working through the many versions of this patchset.
>>
>> Update: I had to drop "gitlab-ci: Check building KVM-only aarch64 target"
>> because it enables a CI job that fails on our aarch64 runner
>> (because it wants to run tests using KVM but that machine
>> isn't configured to allow the runner to use KVM).
>
> We fixed the runner config, but the CI still fails on that notcg
> job because it is trying to run tests that explicitly use
> '-accel tcg':
> https://gitlab.com/qemu-project/qemu/-/jobs/4212850809#L3595
>
> Something is weird here, because we built without TCG support
> on an aarch64 host but we still got qemu-system-i386
> and qemu-system-x86_64 binaries, which then don't work
> and cause the tests to fail...
>
Hmm, that's potentially due to Xen. Looks like we need more (!tcg &&
!kvm) checks. Let me try to reproduce it.
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds
2023-05-02 16:23 ` Fabiano Rosas
@ 2023-05-02 17:11 ` Fabiano Rosas
0 siblings, 0 replies; 37+ messages in thread
From: Fabiano Rosas @ 2023-05-02 17:11 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-devel, qemu-arm, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée
Fabiano Rosas <farosas@suse.de> writes:
> Peter Maydell <peter.maydell@linaro.org> writes:
>
>> On Tue, 2 May 2023 at 15:51, Peter Maydell <peter.maydell@linaro.org> wrote:
>>>
>>> On Tue, 2 May 2023 at 10:55, Peter Maydell <peter.maydell@linaro.org> wrote:
>>> >
>>> > On Wed, 26 Apr 2023 at 19:00, Fabiano Rosas <farosas@suse.de> wrote:
>>> > >
>>> > > Hi,
>>> > >
>>> > > Some minor changes:
>>> > >
>>> > > - new patch to move a test under CONFIG_TCG (broken on master);
>>> > > - new patch to document the unsupported CPU test (Philippe);
>>> > > - changed the test skip message when no KVM or TCG are present (Igor).
>>> >
>>> > Applied to target-arm.next; thanks for your persistence in
>>> > working through the many versions of this patchset.
>>>
>>> Update: I had to drop "gitlab-ci: Check building KVM-only aarch64 target"
>>> because it enables a CI job that fails on our aarch64 runner
>>> (because it wants to run tests using KVM but that machine
>>> isn't configured to allow the runner to use KVM).
>>
>> We fixed the runner config, but the CI still fails on that notcg
>> job because it is trying to run tests that explicitly use
>> '-accel tcg':
>> https://gitlab.com/qemu-project/qemu/-/jobs/4212850809#L3595
>>
>> Something is weird here, because we built without TCG support
>> on an aarch64 host but we still got qemu-system-i386
>> and qemu-system-x86_64 binaries, which then don't work
>> and cause the tests to fail...
>>
>
> Hmm, that's potentially due to Xen. Looks like we need more (!tcg &&
> !kvm) checks. Let me try to reproduce it.
Ah right, the test is skipped on my aarch64 host because I don't have
genisomage available. So what we need is this:
-- >8 --
From: Fabiano Rosas <farosas@suse.de>
Date: Tue, 2 May 2023 13:42:14 -0300
Subject: [PATCH] fixup! tests/qtest: Fix tests when no KVM or TCG are present
---
tests/qtest/cdrom-test.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/tests/qtest/cdrom-test.c b/tests/qtest/cdrom-test.c
index 26a2400181..09655e6ff0 100644
--- a/tests/qtest/cdrom-test.c
+++ b/tests/qtest/cdrom-test.c
@@ -205,6 +205,11 @@ int main(int argc, char **argv)
g_test_init(&argc, &argv, NULL);
+ if (!qtest_has_accel("tcg") && !qtest_has_accel("kvm")) {
+ g_test_skip("No KVM or TCG accelerator available");
+ return 0;
+ }
+
if (exec_genisoimg(genisocheck)) {
/* genisoimage not available - so can't run tests */
return g_test_run();
--
2.35.3
^ permalink raw reply related [flat|nested] 37+ messages in thread
end of thread, other threads:[~2023-05-02 17:11 UTC | newest]
Thread overview: 37+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-04-26 18:00 [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 01/13] target/arm: Move cortex sysregs into a separate file Fabiano Rosas
2023-04-28 22:41 ` Philippe Mathieu-Daudé
2023-04-26 18:00 ` [PATCH v11 02/13] target/arm: Remove dead code from cpu_max_set_sve_max_vq Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 03/13] target/arm: Extract TCG -cpu max code into a function Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 04/13] target/arm: Do not expose all -cpu max features to qtests Fabiano Rosas
2023-04-27 9:37 ` Richard Henderson
2023-04-28 22:35 ` Philippe Mathieu-Daudé
2023-05-02 12:23 ` Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 05/13] target/arm: Move 64-bit TCG CPUs into tcg/ Fabiano Rosas
2023-04-28 22:38 ` Philippe Mathieu-Daudé
2023-04-26 18:00 ` [PATCH v11 06/13] tests/qtest: Adjust and document query-cpu-model-expansion test for arm Fabiano Rosas
2023-04-27 8:08 ` Thomas Huth
2023-04-27 9:39 ` Richard Henderson
2023-04-27 13:16 ` Fabiano Rosas
2023-04-28 7:45 ` Richard Henderson
2023-04-28 13:43 ` Fabiano Rosas
2023-05-02 9:46 ` Peter Maydell
2023-04-26 18:00 ` [PATCH v11 07/13] target/arm: move cpu_tcg to tcg/cpu32.c Fabiano Rosas
2023-04-28 22:37 ` Philippe Mathieu-Daudé
2023-04-26 18:00 ` [PATCH v11 08/13] tests/qtest: Fix tests when no KVM or TCG are present Fabiano Rosas
2023-04-27 9:42 ` Richard Henderson
2023-04-27 18:41 ` Michael S. Tsirkin
2023-04-28 22:32 ` Philippe Mathieu-Daudé
2023-04-26 18:00 ` [PATCH v11 09/13] tests/avocado: Pass parameters to migration test Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 10/13] arm/Kconfig: Always select SEMIHOSTING when TCG is present Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 11/13] arm/Kconfig: Do not build TCG-only boards on a KVM-only build Fabiano Rosas
2023-04-26 18:00 ` [PATCH v11 12/13] tests/qtest: Restrict tpm-tis-i2c-test to CONFIG_TCG Fabiano Rosas
2023-04-27 7:00 ` Thomas Huth
2023-04-27 9:44 ` Richard Henderson
2023-04-26 18:00 ` [PATCH v11 13/13] gitlab-ci: Check building KVM-only aarch64 target Fabiano Rosas
2023-04-27 9:46 ` Richard Henderson
2023-05-02 9:55 ` [PATCH v11 00/13] target/arm: Allow CONFIG_TCG=n builds Peter Maydell
2023-05-02 14:51 ` Peter Maydell
2023-05-02 16:07 ` Peter Maydell
2023-05-02 16:23 ` Fabiano Rosas
2023-05-02 17:11 ` Fabiano Rosas
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