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Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::32c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Mark Cave-Ayland , "qemu-devel@nongnu.org" , Programmingkid , "qemu-ppc@nongnu.org" , Howard Spoelstra , Dino Papararo Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" =E7=BD=97=E5=8B=87=E5=88=9A(Yonggang Luo) writes: > On Thu, Apr 30, 2020 at 10:18 AM Richard Henderson < > richard.henderson@linaro.org> wrote: > >> On 4/29/20 5:20 PM, =E7=BD=97=E5=8B=87=E5=88=9A(Yonggang Luo) wrote: >> > Question, in hard-float, if we don't want to read the fp register. >> > for example: If we wanna compute c =3D a + b in fp32 >> > if c =3D a + b In hard float >> > and if b1 =3D c - a in hard float >> > if b1 !=3D b at bitwise level, the we se the inexat to 1, otherwsie >> > we set inexat bit to 0? are this valid? >> > >> > we can also do it for a * b, a - b, a / b. >> > >> >> That does seem plausible, for all of the normal values for which we would >> apply >> the hard-float optimization anyway. But we already check for the >> exceptional >> cases: >> >> if (unlikely(f32_is_inf(ur))) { >> s->float_exception_flags |=3D float_flag_overflow; >> } else if (unlikely(fabsf(ur.h) <=3D FLT_MIN)) { >> if (post =3D=3D NULL || post(ua, ub)) { >> goto soft; >> } >> } >> > I means remove of all thse exceptional cases, and detecting float > exception by hard float operation. When this was originally done it was found to be faster testing for the float conditions in software (which are basically bitops) than reading the FP exception register which can be a high latency operation. --=20 Alex Benn=C3=A9e