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References: <20181025144644.15464-1-cota@braap.org>
	<20181025144644.15464-35-cota@braap.org>
From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
In-reply-to: <20181025144644.15464-35-cota@braap.org>
Date: Wed, 31 Oct 2018 16:35:03 +0000
Message-ID: <87lg6e6pmw.fsf@linaro.org>
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Subject: Re: [Qemu-devel] [RFC v4 35/71] openrisc: use cpu_reset_interrupt
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To: "Emilio G. Cota" <cota@braap.org>
Cc: qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>, Stafford Horne <shorne@gmail.com>, Richard Henderson <richard.henderson@linaro.org>


Emilio G. Cota <cota@braap.org> writes:

> From: Paolo Bonzini <pbonzini@redhat.com>
>
> Cc: Stafford Horne <shorne@gmail.com>
> Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Emilio G. Cota <cota@braap.org>

Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>

> ---
>  target/openrisc/sys_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
> index ab4d8fb520..c645cc896d 100644
> --- a/target/openrisc/sys_helper.c
> +++ b/target/openrisc/sys_helper.c
> @@ -170,7 +170,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulon=
g spr, target_ulong rb)
>                  env->ttmr =3D (rb & ~TTMR_IP) | ip;
>              } else {    /* Clear IP bit.  */
>                  env->ttmr =3D rb & ~TTMR_IP;
> -                cs->interrupt_request &=3D ~CPU_INTERRUPT_TIMER;
> +                cpu_reset_interrupt(cs, CPU_INTERRUPT_TIMER);
>              }
>
>              cpu_openrisc_timer_update(cpu);


--
Alex Benn=C3=A9e