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From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
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Date: Tue, 24 Jan 2017 20:31:37 +0000
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Subject: Re: [Qemu-devel] [PATCH v7 16/27] cputlb: add tlb_flush_by_mmuidx
 async routines
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To: Richard Henderson <rth@twiddle.net>
Cc: mttcg@greensocs.com, qemu-devel@nongnu.org, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com, peter.maydell@linaro.org, claudio.fontana@huawei.com, Peter Crosthwaite <crosthwaite.peter@gmail.com>, jan.kiszka@siemens.com, mark.burton@greensocs.com, serge.fdrv@gmail.com, pbonzini@redhat.com, bamvor.zhangjian@linaro.org


Richard Henderson <rth@twiddle.net> writes:

> On 01/19/2017 09:04 AM, Alex Bennée wrote:
>> +/* Helper function to slurp va_args list into a bitmap
>> + */
>> +static inline unsigned long make_mmu_index_bitmap(va_list args)
>> +{
>> +    unsigned long bitmap = 0;
>> +    int mmu_index = va_arg(args, int);
>> +
>> +    /* An empty va_list would be a bad call */
>> +    g_assert(mmu_index > 0);
>> +
>> +    do {
>> +        set_bit(mmu_index, &bitmap);
>> +        mmu_index = va_arg(args, int);
>> +    } while (mmu_index >= 0);
>> +
>> +    return bitmap;
>> +}
>> +
>
> Why don't we just pass in this bitmap in the first place?  It's much better
> than having to use varargs in tlb_flush_by_mmuidx...

We could. By not messing with the API it leaves the door open to having
other non-MTTCG architectures that have lots of MMU indexes versus a
hard limit based on page-size. That said I think the number of indexes
also affects the size of the TLB so I guess the current design is
limited for arbitrarily large sets if indexes?

Is ARM is the current outlier for this functionality? Apart from SPARC's
two uses are we likely to see more architectures using this?

--
Alex Bennée