From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51363) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aRgg5-0004IF-CJ for qemu-devel@nongnu.org; Fri, 05 Feb 2016 08:44:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aRgg2-0008GU-3o for qemu-devel@nongnu.org; Fri, 05 Feb 2016 08:44:01 -0500 Received: from mail-wm0-x22d.google.com ([2a00:1450:400c:c09::22d]:37245) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aRgg1-0008GM-Sm for qemu-devel@nongnu.org; Fri, 05 Feb 2016 08:43:58 -0500 Received: by mail-wm0-x22d.google.com with SMTP id g62so27838700wme.0 for ; Fri, 05 Feb 2016 05:43:57 -0800 (PST) References: <1454506721-11843-1-git-send-email-peter.maydell@linaro.org> <1454506721-11843-4-git-send-email-peter.maydell@linaro.org> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1454506721-11843-4-git-send-email-peter.maydell@linaro.org> Date: Fri, 05 Feb 2016 13:43:55 +0000 Message-ID: <87lh6znug4.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH 3/7] target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Peter Maydell writes: > The registers MVBAR and SCR should have the behaviour of trapping to > EL3 if accessed from Secure EL1, but we were incorrectly implementing > them to UNDEF (which would trap to EL1). Fix this by using the new > access_trap_aa32s_el1() access function. > > Signed-off-by: Peter Maydell > --- > target-arm/helper.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 8b96b80..d85b04f 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3547,7 +3547,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { > .resetvalue = 0, .writefn = scr_write }, > { .name = "SCR", .type = ARM_CP_ALIAS, > .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, > - .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), > + .access = PL1_RW, .accessfn = access_trap_aa32s_el1, > + .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), > .writefn = scr_write }, > { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, > @@ -3569,7 +3570,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { > .access = PL3_W | PL1_R, .resetvalue = 0, > .fieldoffset = offsetof(CPUARMState, cp15.nsacr) }, > { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, > - .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0, > + .access = PL1_RW, .accessfn = access_trap_aa32s_el1, > + .writefn = vbar_write, .resetvalue = 0, > .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, > { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, > .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */ Reviewed-by: Alex Bennée -- Alex Bennée